# CA3140AEZ

**RENESAS** · Operational Amplifier · PDIP-8

CA3140AEZ from RENESAS, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OFFSET NULL | passive | Offset-null terminal provided for input offset voltage nulling, used together with pin 5. |
| 2 | INV. INPUT | input | Inverting input of the PMOS-input operational amplifier, with very low input current (typically 10 pA at 15 V) and common-mode range extending 0.5 V below the negative supply. |
| 3 | NON-INV. INPUT | input | Non-inverting input whose common-mode voltage can be swung 0.5 V below the negative supply terminal. |
| 4 | V- | power_in | Negative supply terminal; the device operates from 4 V to 36 V total supply, single or dual. |
| 5 | OFFSET NULL | passive | Second offset-null terminal used with pin 1 for input offset voltage nulling. |
| 6 | OUTPUT | output | Output of the bipolar output stage, which has built-in protection against load short circuit to either supply rail or to ground. |
| 7 | V+ | power_in | Positive supply terminal; the device operates from 4 V to 36 V total supply, single or dual. |
| 8 | STROBE | input | Strobe terminal as labelled in the pinout figure; the provided datasheet text gives no function or limits for it. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | PDIP-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | /VIO/ |  | 2 | 5 | mV | VSUPPLY = 15V, TA = 25oC | 3 |
| Input Offset Current | /IIO/ |  | 0.5 | 20 | pA | VSUPPLY = 15V, TA = 25oC | 3 |
| Input Current | II |  | 10 | 40 | pA | VSUPPLY = 15V, TA = 25oC | 3 |
| Large Signal Voltage Gain | AOL | 20 | 100 |  | kV/V | VSUPPLY = 15V, TA = 25oC; Note 3 (VO = 26VP-P, +12V, -14V, RL = 2k) | 4 |
| Large Signal Voltage Gain | AOL | 86 | 100 |  | dB | VSUPPLY = 15V, TA = 25oC; Note 3 (VO = 26VP-P, +12V, -14V, RL = 2k) | 4 |
| Common Mode Rejection Ratio | CMRR |  | 32 | 320 | V/V | VSUPPLY = 15V, TA = 25oC; See Figure 34 | 4 |
| Common Mode Rejection Ratio | CMRR | 70 | 90 |  | dB | VSUPPLY = 15V, TA = 25oC; See Figure 34 | 4 |
| Common Mode Input Voltage Range | VICR | -15 |  | 12 | V | VSUPPLY = 15V, TA = 25oC; See Figure 8 | 4 |
| Power-Supply Rejection Ratio | PSRR |  | 100 | 150 | V/V | VSUPPLY = 15V, TA = 25oC; VIO/VS (See Figure 36) | 4 |
| Power-Supply Rejection Ratio | PSRR | 76 | 80 |  | dB | VSUPPLY = 15V, TA = 25oC; VIO/VS (See Figure 36) | 4 |
| Max Output Voltage | VOM+ | 12 | 13 |  | V | VSUPPLY = 15V, TA = 25oC; Note 4 (RL = 2k); See Figures 2, 8 | 4 |
| Max Output Voltage | VOM- | -14 | -14.4 |  | V | VSUPPLY = 15V, TA = 25oC; Note 4 (RL = 2k); See Figures 2, 8 | 4 |
| Supply Current | I+ |  | 4 | 6 | mA | VSUPPLY = 15V, TA = 25oC; See Figure 32 | 4 |
| Device Dissipation | PD |  | 120 | 180 | mW | VSUPPLY = 15V, TA = 25oC | 4 |
| Input Offset Voltage Temperature Drift | VIO/T |  | 6 |  | V/oC | VSUPPLY = 15V, TA = 25oC | 4 |
| DC Supply Voltage (between V+ and V-) |  |  |  | 36 | V |  | 3 |
| Differential Mode Input Voltage |  |  |  | 8 | V |  | 3 |
| Input Terminal Current |  |  |  | 1 | mA |  | 3 |
| Maximum Junction Temperature (Plastic Package) |  |  |  | 150 | oC |  | 3 |
| Maximum Storage Temperature Range |  | -65 |  | 150 | oC |  | 3 |
| Maximum Lead Temperature (Soldering) |  |  |  | 300 | oC | Soldering 10s | 3 |
| Supply Voltage Range (single or dual supply) |  | 4 |  | 36 | V | Single or dual supply; stated in the device overview | 1 |
| Temperature Range |  | -55 |  | 125 | oC | Operating temperature range | 3 |
| Thermal Resistance Junction-to-Ambient (PDIP) | θJA |  | 115 |  | oC/W | Typical, Note 1 (low effective thermal conductivity test board, free air); PDIP package | 3 |

## CAD (KiCad official)

- Symbol: `CA3140AEZ`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files: `ca3140aez-etched.step` / `ca3140aez-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca3140aez.step` / `ca3140aez.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589015628057890816) (24 pp, sha256 `347283cf7158b196`, retrieved 2026-10-16, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ca3140aez-datasheet.pdf)