component

CA-IS3831LW

Public Made by Adom

by adom

Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentisolatorsca-is3831lwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CA-IS3831LW

Chipanalog · Digital Isolators · SOIC-16-300mil

CA-IS3831LW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage, 2.375 V to 5.5 V recommended (7.0 V absolute maximum), bypassed with a 0.1 µF to 1 µF capacitor.
2 GNDA power_in Side A ground reference.
3 VI1 input Side A logic input for channel 1, Schmitt-trigger input with a 2 V high / 0.8 V low threshold.
4 VI2 input Side A logic input for channel 2, Schmitt-trigger input with a 2 V high / 0.8 V low threshold.
5 VO3 output Side A logic output of the reverse channel 3 on CA-IS3831, enabled by ENA.
6 NC unconnected No internal connection; may be left floating or connected to VDD or GND.
7 ENA input Side A output enable for VO3, active high or floating, internally pulled up to local VDD; low puts VO3 in high impedance.
8 GNDA power_in Side A ground reference.
9 GNDB power_in Side B ground reference.
10 ENB input Side B output enable for VO1 and VO2, active high or floating, internally pulled up to local VDD; low puts VO1 and VO2 in high impedance.
11 NC unconnected No internal connection; may be left floating or connected to VDD or GND.
12 VI3 input Side B logic input of the reverse channel 3 on CA-IS3831, Schmitt-trigger input with a 2 V high / 0.8 V low threshold.
13 VO2 output Side B logic output for channel 2, rail-to-rail with about 50 Ω output impedance, drives up to 4 mA at 5 V.
14 VO1 output Side B logic output for channel 1, rail-to-rail with about 50 Ω output impedance, drives up to 4 mA at 5 V.
15 GNDB power_in Side B ground reference.
16 VDDB power_in Side B supply voltage, 2.375 V to 5.5 V recommended (7.0 V absolute maximum), bypassed with a 0.1 µF to 1 µF capacitor.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Isolators
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB -0.5 7 V 5
Input voltage Ax, Bx, ENx Vin -0.5 V max VDD+0.5, not to exceed 7 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature TSTG -65 150 °C 5
ESD HBM VESD -8000 8000 V ANSI/ESDA/JEDEC JS-001, all pins 5
ESD CDM VESD -2000 2000 V JESD22-C101, all pins 5
Supply voltage VDDA, VDDB 2.375 5.5 V 5
UVLO rising threshold VDD(UVLO+) 1.95 2.24 2.375 V 5
UVLO falling threshold VDD(UVLO-) 1.88 2.1 2.325 V 5
UVLO hysteresis VHYS(UVLO) 70 140 250 mV 5
High-level output current IOH -4 mA VDDO = 5V (-2 at 3.3V, -1 at 2.5V) 5
Low-level output current IOL 4 mA VDDO = 5V (2 at 3.3V, 1 at 2.5V) 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signaling rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Junction-to-ambient thermal resistance RθJA 83.4 °C/W W package 6
Maximum power dissipation PD 252 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave input 6
Max power dissipation side A PDA 92 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C 6
Max power dissipation side B PDB 160 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C 6
Output voltage high VOH 4.8 V VDD=5V ±10%, IOH = -4mA; min VDDO-0.4 9
Output voltage low VOL 0.2 0.4 V VDD=5V ±10%, IOL = 4mA 9
Output voltage high VOH 3.1 V VDD=3.3V ±10%, IOH = -2mA; min VDDO-0.4 9
Input high threshold VIT+(IN) 2 V 9
Input low threshold VIT-(IN) 0.8 V 9
Input high leakage current IIH 20 µA VIH = VDDA at Ax or Bx or ENx 9
Input low leakage current IIL -20 µA VIL = 0 V at Ax or Bx 9
Output impedance ZO 50 Ω 9
Common-mode transient immunity CMTI 100 150 kV/µs VI = VDDI or 0 V, VCM = 1200 V 9
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V 9
IDDA disable, VIN=0V IDDA 1.6 3.1 mA 5V; ENA = ENB = 0 V; VIN = 0V (CA-IS3831L) 10
IDDB disable, VIN=0V IDDB 2 3.6 mA 5V; ENA = ENB = 0 V; VIN = 0V (CA-IS3831L) 10
IDDA disable, VIN=VDDI IDDA 4.1 6.5 mA 5V; ENA = ENB = 0 V; VIN = VDDI (CA-IS3831L) 10
IDDB disable, VIN=VDDI IDDB 3.2 5.3 mA 5V; ENA = ENB = 0 V; VIN = VDDI (CA-IS3831L) 10
IDDA DC, VIN=0V IDDA 1.6 3.3 mA 5V; ENA = ENB = VDDI; VIN = 0V (CA-IS3831L) 10
IDDB DC, VIN=0V IDDB 2.1 3.8 mA 5V; ENA = ENB = VDDI; VIN = 0V (CA-IS3831L) 10
IDDA DC, VIN=VDDI IDDA 4.2 6.6 mA 5V; ENA = ENB = VDDI; VIN = VDDI (CA-IS3831L) 10
IDDB DC, VIN=VDDI IDDB 3.4 5.5 mA 5V; ENA = ENB = VDDI; VIN = VDDI (CA-IS3831L) 10
IDDA 1Mbps IDDA 2.7 4.1 mA 5V; 1Mbps (500kHz), CL = 15 pF 10
IDDB 1Mbps IDDB 3.2 4.8 mA 5V; 1Mbps (500kHz), CL = 15 pF 10
IDDA 10Mbps IDDA 6.5 9.1 mA 5V; 10Mbps (5MHz), CL = 15 pF 10
IDDB 10Mbps IDDB 10.5 15.8 mA 5V; 10Mbps (5MHz), CL = 15 pF 10
IDDA 100Mbps IDDA 12.9 18.5 mA 5V; 100Mbps (50MHz), CL = 15 pF 10
IDDB 100Mbps IDDB 22.4 36 mA 5V; 100Mbps (50MHz), CL = 15 pF 10
Data rate DR 0 150 Mbps VDD=5V ±10% 13
Minimum pulse width PWmin 5 ns VDD=5V ±10% 13
Propagation delay tPLH, tPHL 12 15 ns VDD=5V ±10%; Figure 8-1 13
Pulse width distortion PWD 0.2 4.5 ns VDD=5V ±10%; /tPLH - tPHL/ 13
Channel-to-channel output skew tsk(o) 0.4 2.5 ns VDD=5V ±10%; same-direction channels 13
Part-to-part skew tsk(pp) 2 4.5 ns VDD=5V ±10% 13
Output rise time tr 2.5 4 ns VDD=5V ±10%; Figure 8-1 13
Output fall time tf 2.5 4 ns VDD=5V ±10%; Figure 8-1 13
Disable propagation delay, high to Hi-Z tPHZ 12 20 ns VDD=5V ±10%; Figure 8-2 13
Disable propagation delay, low to Hi-Z tPLZ 12 20 ns VDD=5V ±10%; Figure 8-2 13
Enable propagation delay, Hi-Z to high tPZH 15 25 ns VDD=5V ±10%; Figure 8-2 13
Enable propagation delay, Hi-Z to low tPZL 15 25 ns VDD=5V ±10%; Figure 8-2 13
Default output delay from UVLO tDO 8 12 µs VDD=5V ±10%; Figure 8-3 13
Start-up time tSU 15 40 µs VDD=5V ±10% 13
Propagation delay 3.3V tPLH, tPHL 12 17 ns VDD=3.3V ±10%; Figure 8-1 13

CAD (KiCad official)

  • Symbol: CA-IS3831LW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3831lw-etched.step / ca-is3831lw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3831lw.step / ca-is3831lw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (24 pp, sha256 2fb032ffaaf8a680, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF