# CA-IS3763LN

**Chipanalog** · Digital Isolators · SOIC-16

CA-IS3763LN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side power supply input, 2.375 V to 5.5 V recommended operating range |
| 2 | VI1 | input | A-side isolated logic input with Schmitt trigger, VIH ≥ 2V minimum and VIL ≤ 0.8V maximum |
| 3 | VI2 | input | A-side isolated logic input with Schmitt trigger, VIH ≥ 2V minimum and VIL ≤ 0.8V maximum |
| 4 | VI3 | input | A-side isolated logic input with Schmitt trigger, VIH ≥ 2V minimum and VIL ≤ 0.8V maximum |
| 5 | VO4 | output | A-side isolated logic output with 50Ω impedance and ±4mA drive capacity at 5V supply |
| 6 | VO5 | output | A-side isolated logic output with 50Ω impedance and ±4mA drive capacity at 5V supply |
| 7 | VO6 | output | A-side isolated logic output with 50Ω impedance and ±4mA drive capacity at 5V supply |
| 8 | GNDA | power_in | A-side ground reference point isolated from B-side across capacitive barrier |
| 9 | GNDB | power_in | B-side ground reference point isolated from A-side across capacitive barrier |
| 10 | VI6 | input | B-side isolated logic input with Schmitt trigger, VIH ≥ 2V minimum and VIL ≤ 0.8V maximum |
| 11 | VI5 | input | B-side isolated logic input with Schmitt trigger, VIH ≥ 2V minimum and VIL ≤ 0.8V maximum |
| 12 | VI4 | input | B-side isolated logic input with Schmitt trigger, VIH ≥ 2V minimum and VIL ≤ 0.8V maximum |
| 13 | VO3 | output | B-side isolated logic output with 50Ω impedance and ±4mA drive capacity at 5V supply |
| 14 | VO2 | output | B-side isolated logic output with 50Ω impedance and ±4mA drive capacity at 5V supply |
| 15 | VO1 | output | B-side isolated logic output with 50Ω impedance and ±4mA drive capacity at 5V supply |
| 16 | VDDB | power_in | B-side power supply input, 2.375 V to 5.5 V recommended operating range |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `CA-IS3763LN`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `ca-is3763ln-etched.step` / `ca-is3763ln-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is3763ln.step` / `ca-is3763ln.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590239271903784960) (23 pp, sha256 `5297fd5a42777b27`, retrieved 2026-09-21, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ca-is3763ln-datasheet.pdf)