main
Ray Publish 0.1.0 c8a4d06 12d ago
{
  "slug": "ca-is3763hb",
  "version": "0.1.0",
  "type": "component",
  "description": "Chipanalog Digital Isolators, SSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "signal isolation devices",
    "ca-is3763hb",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ca-is3763hb.kicad_sym",
    "ca-is3763hb.kicad_mod",
    "ca-is3763hb.glb",
    "ca-is3763hb.step",
    "ca-is3763hb.lbr",
    "docs/hero.png",
    "docs/ca-is3763hb-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ca-is3763hb-hero.glb",
    "ca-is3763hb-hero.overlay.json",
    "ca-is3763hb-etched.glb"
  ],
  "component": {
    "mpn": "CA-IS3763HB",
    "manufacturer": "Chipanalog",
    "package": "SSOP-16",
    "pin_count": 16,
    "category": "Signal Isolation Devices",
    "subcategory": "Digital Isolators",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590902618804215808",
    "parts": {
      "symbol": "ca-is3763hb.kicad_sym",
      "footprint": "ca-is3763hb.kicad_mod",
      "model_3d": "ca-is3763hb-hero.glb",
      "model_3d_plain": "ca-is3763hb-etched.glb",
      "model_3d_step": "ca-is3763hb-etched.step",
      "model_3d_step_plain": "ca-is3763hb.step",
      "lbr": "ca-is3763hb.lbr"
    },
    "distributor_links": {
      "lcsc": "C5457088"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T23:07:31Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDDA",
        "type": "power_in",
        "description": "Side-A supply voltage; recommended 2.375 V to 5.5 V, absolute maximum 7.0 V referenced to GNDA, and a 0.1 µF to 1 µF bypass capacitor is required."
      },
      {
        "number": "2",
        "name": "VI1",
        "type": "input",
        "description": "Side-A logic input for forward channel 1 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "3",
        "name": "VI2",
        "type": "input",
        "description": "Side-A logic input for forward channel 2 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "4",
        "name": "VI3",
        "type": "input",
        "description": "Side-A logic input for forward channel 3 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "5",
        "name": "VO4",
        "type": "output",
        "description": "Side-A logic output of reverse channel 4, which follows the side-B input VI4 (pin 12); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance."
      },
      {
        "number": "6",
        "name": "VO5",
        "type": "output",
        "description": "Side-A logic output of reverse channel 5, which follows the side-B input VI5 (pin 11); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance."
      },
      {
        "number": "7",
        "name": "VO6",
        "type": "output",
        "description": "Side-A logic output of reverse channel 6, which follows the side-B input VI6 (pin 10); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance."
      },
      {
        "number": "8",
        "name": "GNDA",
        "type": "power_in",
        "description": "Side-A ground reference for VDDA and the side-A logic signals."
      },
      {
        "number": "9",
        "name": "GNDB",
        "type": "power_in",
        "description": "Side-B ground reference for VDDB and the side-B logic signals, isolated from GNDA."
      },
      {
        "number": "10",
        "name": "VI6",
        "type": "input",
        "description": "Side-B logic input for reverse channel 6 (B to A), which drives output VO6 (pin 7); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "11",
        "name": "VI5",
        "type": "input",
        "description": "Side-B logic input for reverse channel 5 (B to A), which drives output VO5 (pin 6); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "12",
        "name": "VI4",
        "type": "input",
        "description": "Side-B logic input for reverse channel 4 (B to A), which drives output VO4 (pin 5); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V."
      },
      {
        "number": "13",
        "name": "VO3",
        "type": "output",
        "description": "Side-B logic output of forward channel 3 (A to B), which follows side-A input VI3 (pin 4); output drive is 4 mA at 5 V with about 50 Ω output impedance."
      },
      {
        "number": "14",
        "name": "VO2",
        "type": "output",
        "description": "Side-B logic output of forward channel 2 (A to B), which follows side-A input VI2 (pin 3); output drive is 4 mA at 5 V with about 50 Ω output impedance."
      },
      {
        "number": "15",
        "name": "VO1",
        "type": "output",
        "description": "Side-B logic output of forward channel 1 (A to B), which follows side-A input VI1 (pin 2); output drive is 4 mA at 5 V with about 50 Ω output impedance."
      },
      {
        "number": "16",
        "name": "VDDB",
        "type": "power_in",
        "description": "Side-B supply voltage; recommended 2.375 V to 5.5 V, absolute maximum 7.0 V referenced to GNDB, and a 0.1 µF to 1 µF bypass capacitor is required."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Table 6-1 labels pin 12 as 'VO4' (the CA-IS3760/62 name), but for CA-IS3763 the same row and the CA-; Pins 5-7 and 10-11 are dual-function across the CA-IS376x family in the datasheet. Pin names and dir; The datasheet's pinout is the same for the HB (default-high) and LB (default-low) suffixes. The H su"
        ],
        "pages_sent": 22,
        "cost_usd": 0.122,
        "at": "2026-10-18T23:05:28"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590902618804215808",
        "pages": 22,
        "sha256": "0d88c3748184ff45",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ca-is3763hb.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.8,
          6.2,
          2.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d0e11e46aeca5dbaa5c4bb538f3f4899761267cabdeba6486325ae9e979c03ef",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ca-is3763hb-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          7.8,
          6.2,
          2.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "f66cfe96da2bd9fe84cb3d2f74c9f82a2edf60f0031d90a7b244c3830024ea09",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}