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CA-IS3763HB
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Chipanalog Digital Isolators, SSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CA-IS3763HB
Chipanalog · Digital Isolators · SSOP-16
CA-IS3763HB from Chipanalog, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side-A supply voltage; recommended 2.375 V to 5.5 V, absolute maximum 7.0 V referenced to GNDA, and a 0.1 µF to 1 µF bypass capacitor is required. |
| 2 | VI1 | input | Side-A logic input for forward channel 1 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 3 | VI2 | input | Side-A logic input for forward channel 2 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 4 | VI3 | input | Side-A logic input for forward channel 3 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 5 | VO4 | output | Side-A logic output of reverse channel 4, which follows the side-B input VI4 (pin 12); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance. |
| 6 | VO5 | output | Side-A logic output of reverse channel 5, which follows the side-B input VI5 (pin 11); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance. |
| 7 | VO6 | output | Side-A logic output of reverse channel 6, which follows the side-B input VI6 (pin 10); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance. |
| 8 | GNDA | power_in | Side-A ground reference for VDDA and the side-A logic signals. |
| 9 | GNDB | power_in | Side-B ground reference for VDDB and the side-B logic signals, isolated from GNDA. |
| 10 | VI6 | input | Side-B logic input for reverse channel 6 (B to A), which drives output VO6 (pin 7); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 11 | VI5 | input | Side-B logic input for reverse channel 5 (B to A), which drives output VO5 (pin 6); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 12 | VI4 | input | Side-B logic input for reverse channel 4 (B to A), which drives output VO4 (pin 5); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 13 | VO3 | output | Side-B logic output of forward channel 3 (A to B), which follows side-A input VI3 (pin 4); output drive is 4 mA at 5 V with about 50 Ω output impedance. |
| 14 | VO2 | output | Side-B logic output of forward channel 2 (A to B), which follows side-A input VI2 (pin 3); output drive is 4 mA at 5 V with about 50 Ω output impedance. |
| 15 | VO1 | output | Side-B logic output of forward channel 1 (A to B), which follows side-A input VI1 (pin 2); output drive is 4 mA at 5 V with about 50 Ω output impedance. |
| 16 | VDDB | power_in | Side-B supply voltage; recommended 2.375 V to 5.5 V, absolute maximum 7.0 V referenced to GNDB, and a 0.1 µF to 1 µF bypass capacitor is required. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SSOP-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB (absolute maximum) | VDDA, VDDB | -0.5 | 7 | V | Relative to GNDA or GNDB, peak values | 5 | |
| Input voltage Ax, Bx (absolute maximum) | Vin | -0.5 | V | Max printed as VDD+0.5 (footnote 3: must not exceed 7 V) | 5 | ||
| Output current IO (absolute maximum) | IO | -20 | 20 | mA | 5 | ||
| Junction temperature TJ (absolute maximum) | TJ | 150 | °C | 5 | |||
| Storage temperature range TSTG (absolute maximum) | TSTG | -65 | 150 | °C | 5 | ||
| Power supply voltage VDDA, VDDB (recommended) | VDDA, VDDB | 2.375 | 5.5 | V | Typ printed as 3.3/5.0 | 5 | |
| VDD undervoltage threshold, rising (UVLO+) | VDD(UVLO+) | 1.95 | 2.24 | 2.375 | V | 5 | |
| VDD undervoltage threshold, falling (UVLO-) | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | 5 | |
| VDD undervoltage hysteresis (UVLO) | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level output current IOH | IOH | -4 | mA | VDDO1 = 5V | 5 | ||
| High-level output current IOH | IOH | -2 | mA | VDDO = 3.3V | 5 | ||
| High-level output current IOH | IOH | -1 | mA | VDDO = 2.5V | 5 | ||
| Low-level output current IOL | IOL | 4 | mA | VDDO = 5V | 5 | ||
| Low-level output current IOL | IOL | 2 | mA | VDDO = 3.3V | 5 | ||
| Low-level output current IOL | IOL | 1 | mA | VDDO = 2.5V | 5 | ||
| Input threshold logic high VIH | VIH | 2 | V | 5 | |||
| Input threshold logic low VIL | VIL | 0.8 | V | 5 | |||
| Signal data rate DR (recommended) | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature TA (recommended) | TA | -40 | 27 | 125 | °C | 5 | |
| Output high voltage VOL-side pair: output low voltage VOL (5V) | VOL | 0.2 | 0.4 | V | IOL = 4mA; 图 8-1 | 9 | |
| Input threshold logic high VIT+(IN) (5V) | VIT+(IN) | 2 | V | VDDA = VDDB = 5 V ± 10% | 9 | ||
| Input threshold logic low VIT-(IN) (5V) | VIT-(IN) | 0.8 | V | VDDA = VDDB = 5 V ± 10% | 9 | ||
| Input high leakage current IIH (5V) | IIH | 20 | µA | VIH = VDDA at Ax or Bx | 9 | ||
| Input low leakage current IIL (5V) | IIL | -20 | µA | VIL = 0 V at Ax or Bx | 9 | ||
| Common-mode transient immunity CMTI (5V) | CMTI | 50 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 9 | ||
| Output low voltage VOL (3.3V) | VOL | 0.2 | 0.4 | V | IOL = 2mA; 图 8-1 | 9 | |
| Input threshold logic high VIT+(IN) (3.3V) | VIT+(IN) | 2 | V | VDDA = VDDB = 3.3 V ± 10% | 9 | ||
| Input threshold logic low VIT-(IN) (3.3V) | VIT-(IN) | 0.8 | V | VDDA = VDDB = 3.3 V ± 10% | 9 | ||
| Input high leakage current IIH (3.3V) | IIH | 20 | µA | VIH = VDDA at Ax or Bx | 9 | ||
| Input low leakage current IIL (3.3V) | IIL | -20 | µA | VIL = 0 V at Ax or Bx | 9 | ||
| Common-mode transient immunity CMTI (3.3V) | CMTI | 50 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 9 | ||
| Output low voltage VOL (2.5V) | VOL | 0.2 | 0.4 | V | IOL = 1mA; 图 8-1 | 9 | |
| Input threshold logic high VIT+(IN) (2.5V) | VIT+(IN) | 2 | V | VDDA = VDDB = 2.5 V ± 5% | 9 | ||
| Input threshold logic low VIT-(IN) (2.5V) | VIT-(IN) | 0.8 | V | VDDA = VDDB = 2.5 V ± 5% | 9 | ||
| Input high leakage current IIH (2.5V) | IIH | 20 | µA | VIH = VDDA at Ax or Bx | 9 | ||
| Input low leakage current IIL (2.5V) | IIL | -20 | µA | VIL = 0 V at Ax or Bx | 9 | ||
| Common-mode transient immunity CMTI (2.5V) | CMTI | 50 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 9 | ||
| Minimum pulse width PWmin (5V) | PWmin | 5 | ns | 13 | |||
| Propagation delay (5V) | tPLH, tPHL | 5 | 12 | 15 | ns | 图 8-1 | 13 |
| Pulse width distortion PWD (5V) | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 13 | |
| Channel-to-channel output skew tsk(o) (5V) | tsk(o) | 0.4 | 2.5 | ns | Same-direction channels (note 1) | 13 | |
| Part-to-part output skew tsk(pp) (5V) | tsk(pp) | 2 | 4.5 | ns | note 2 | 13 | |
| Output rise time tr (5V) | tr | 2.5 | 4 | ns | 图 8-1 | 13 | |
| Output fall time tf (5V) | tf | 2.5 | 4 | ns | 图 8-1 | 13 | |
| Default output delay time tDO (5V) | tDO | 8 | 12 | ns | 图 8-2 | 13 | |
| Start-up time tSU (5V) | tSU | 15 | 40 | µs | 13 | ||
| Supply current IDDA, DC signal (5V, H variant) | IDDA | 2.9 | 4.4 | mA | DC signal; VIN = VDDI1 (CA-IS3763H) | 10 | |
| Supply current IDDB, DC signal (5V, H variant) | IDDB | 2.9 | 4.4 | mA | DC signal; VIN = VDDI1 (CA-IS3763H) | 10 | |
| Supply current IDDA, DC signal (5V, H variant) | IDDA | 5.5 | 8.4 | mA | DC signal; VIN = 0V (CA-IS3763H) | 10 | |
| Supply current IDDB, DC signal (5V, H variant) | IDDB | 5.5 | 8.4 | mA | DC signal; VIN = 0V (CA-IS3763H) | 10 | |
| Supply current IDDA, AC signal (5V, H variant) | IDDA | 4.3 | 6.5 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 1Mbps (500kHz) | 10 | |
| Supply current IDDB, AC signal (5V, H variant) | IDDB | 4.3 | 6.5 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 1Mbps (500kHz) | 10 | |
| Supply current IDDA, AC signal (5V, H variant) | IDDA | 5.7 | 8.4 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 10Mbps (5MHz) | 10 | |
| Supply current IDDB, AC signal (5V, H variant) | IDDB | 5.7 | 8.4 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 10Mbps (5MHz) | 10 | |
| Supply current IDDA, AC signal (5V, H variant) | IDDA | 19.9 | 30 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Supply current IDDB, AC signal (5V, H variant) | IDDB | 19.9 | 30 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Thermal resistance junction-to-ambient RθJA | RθJA | 110 | °C/W | 5 | |||
| High-level output voltage VOH (5V) | VOH | 4.8 | V | IOH = -4mA; 图 8-1 | 9 | ||
| Output impedance ZO (5V) | ZO | 50 | Ω | 9 | |||
| Input capacitance CI (5V) | CI | 2 | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 9 |
CAD (KiCad official)
- Symbol:
CA-IS3763HB - Footprint:
Package_SO:SSOP-16_5.3x6.2mm_P0.65mm - 3D model: SSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ca-is3763hb-etched.step/ca-is3763hb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3763hb.step/ca-is3763hb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (22 pp, sha256
0d88c3748184ff45, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CA-IS3763HB
**Chipanalog** · Digital Isolators · SSOP-16
CA-IS3763HB from Chipanalog, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side-A supply voltage; recommended 2.375 V to 5.5 V, absolute maximum 7.0 V referenced to GNDA, and a 0.1 µF to 1 µF bypass capacitor is required. |
| 2 | VI1 | input | Side-A logic input for forward channel 1 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 3 | VI2 | input | Side-A logic input for forward channel 2 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 4 | VI3 | input | Side-A logic input for forward channel 3 (A to B); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 5 | VO4 | output | Side-A logic output of reverse channel 4, which follows the side-B input VI4 (pin 12); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance. |
| 6 | VO5 | output | Side-A logic output of reverse channel 5, which follows the side-B input VI5 (pin 11); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance. |
| 7 | VO6 | output | Side-A logic output of reverse channel 6, which follows the side-B input VI6 (pin 10); output drive is 4 mA at 5 V (IOH −4 mA, IOL 4 mA) with about 50 Ω output impedance. |
| 8 | GNDA | power_in | Side-A ground reference for VDDA and the side-A logic signals. |
| 9 | GNDB | power_in | Side-B ground reference for VDDB and the side-B logic signals, isolated from GNDA. |
| 10 | VI6 | input | Side-B logic input for reverse channel 6 (B to A), which drives output VO6 (pin 7); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 11 | VI5 | input | Side-B logic input for reverse channel 5 (B to A), which drives output VO5 (pin 6); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 12 | VI4 | input | Side-B logic input for reverse channel 4 (B to A), which drives output VO4 (pin 5); TTL-compatible, with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 13 | VO3 | output | Side-B logic output of forward channel 3 (A to B), which follows side-A input VI3 (pin 4); output drive is 4 mA at 5 V with about 50 Ω output impedance. |
| 14 | VO2 | output | Side-B logic output of forward channel 2 (A to B), which follows side-A input VI2 (pin 3); output drive is 4 mA at 5 V with about 50 Ω output impedance. |
| 15 | VO1 | output | Side-B logic output of forward channel 1 (A to B), which follows side-A input VI1 (pin 2); output drive is 4 mA at 5 V with about 50 Ω output impedance. |
| 16 | VDDB | power_in | Side-B supply voltage; recommended 2.375 V to 5.5 V, absolute maximum 7.0 V referenced to GNDB, and a 0.1 µF to 1 µF bypass capacitor is required. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SSOP-16 |
| Category | Signal Isolation Devices |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB (absolute maximum) | VDDA, VDDB | -0.5 | | 7 | V | Relative to GNDA or GNDB, peak values | 5 |
| Input voltage Ax, Bx (absolute maximum) | Vin | -0.5 | | | V | Max printed as VDD+0.5 (footnote 3: must not exceed 7 V) | 5 |
| Output current IO (absolute maximum) | IO | -20 | | 20 | mA | | 5 |
| Junction temperature TJ (absolute maximum) | TJ | | | 150 | °C | | 5 |
| Storage temperature range TSTG (absolute maximum) | TSTG | -65 | | 150 | °C | | 5 |
| Power supply voltage VDDA, VDDB (recommended) | VDDA, VDDB | 2.375 | | 5.5 | V | Typ printed as 3.3/5.0 | 5 |
| VDD undervoltage threshold, rising (UVLO+) | VDD(UVLO+) | 1.95 | 2.24 | 2.375 | V | | 5 |
| VDD undervoltage threshold, falling (UVLO-) | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | | 5 |
| VDD undervoltage hysteresis (UVLO) | VHYS(UVLO) | 70 | 140 | 250 | mV | | 5 |
| High-level output current IOH | IOH | -4 | | | mA | VDDO1 = 5V | 5 |
| High-level output current IOH | IOH | -2 | | | mA | VDDO = 3.3V | 5 |
| High-level output current IOH | IOH | -1 | | | mA | VDDO = 2.5V | 5 |
| Low-level output current IOL | IOL | | | 4 | mA | VDDO = 5V | 5 |
| Low-level output current IOL | IOL | | | 2 | mA | VDDO = 3.3V | 5 |
| Low-level output current IOL | IOL | | | 1 | mA | VDDO = 2.5V | 5 |
| Input threshold logic high VIH | VIH | 2 | | | V | | 5 |
| Input threshold logic low VIL | VIL | | | 0.8 | V | | 5 |
| Signal data rate DR (recommended) | DR | 0 | | 150 | Mbps | | 5 |
| Ambient temperature TA (recommended) | TA | -40 | 27 | 125 | °C | | 5 |
| Output high voltage VOL-side pair: output low voltage VOL (5V) | VOL | | 0.2 | 0.4 | V | IOL = 4mA; 图 8-1 | 9 |
| Input threshold logic high VIT+(IN) (5V) | VIT+(IN) | 2 | | | V | VDDA = VDDB = 5 V ± 10% | 9 |
| Input threshold logic low VIT-(IN) (5V) | VIT-(IN) | | | 0.8 | V | VDDA = VDDB = 5 V ± 10% | 9 |
| Input high leakage current IIH (5V) | IIH | | | 20 | µA | VIH = VDDA at Ax or Bx | 9 |
| Input low leakage current IIL (5V) | IIL | -20 | | | µA | VIL = 0 V at Ax or Bx | 9 |
| Common-mode transient immunity CMTI (5V) | CMTI | 50 | | | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 9 |
| Output low voltage VOL (3.3V) | VOL | | 0.2 | 0.4 | V | IOL = 2mA; 图 8-1 | 9 |
| Input threshold logic high VIT+(IN) (3.3V) | VIT+(IN) | 2 | | | V | VDDA = VDDB = 3.3 V ± 10% | 9 |
| Input threshold logic low VIT-(IN) (3.3V) | VIT-(IN) | | | 0.8 | V | VDDA = VDDB = 3.3 V ± 10% | 9 |
| Input high leakage current IIH (3.3V) | IIH | | | 20 | µA | VIH = VDDA at Ax or Bx | 9 |
| Input low leakage current IIL (3.3V) | IIL | -20 | | | µA | VIL = 0 V at Ax or Bx | 9 |
| Common-mode transient immunity CMTI (3.3V) | CMTI | 50 | | | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 9 |
| Output low voltage VOL (2.5V) | VOL | | 0.2 | 0.4 | V | IOL = 1mA; 图 8-1 | 9 |
| Input threshold logic high VIT+(IN) (2.5V) | VIT+(IN) | 2 | | | V | VDDA = VDDB = 2.5 V ± 5% | 9 |
| Input threshold logic low VIT-(IN) (2.5V) | VIT-(IN) | | | 0.8 | V | VDDA = VDDB = 2.5 V ± 5% | 9 |
| Input high leakage current IIH (2.5V) | IIH | | | 20 | µA | VIH = VDDA at Ax or Bx | 9 |
| Input low leakage current IIL (2.5V) | IIL | -20 | | | µA | VIL = 0 V at Ax or Bx | 9 |
| Common-mode transient immunity CMTI (2.5V) | CMTI | 50 | | | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 9 |
| Minimum pulse width PWmin (5V) | PWmin | 5 | | | ns | | 13 |
| Propagation delay (5V) | tPLH, tPHL | 5 | 12 | 15 | ns | 图 8-1 | 13 |
| Pulse width distortion PWD (5V) | PWD | | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 13 |
| Channel-to-channel output skew tsk(o) (5V) | tsk(o) | | 0.4 | 2.5 | ns | Same-direction channels (note 1) | 13 |
| Part-to-part output skew tsk(pp) (5V) | tsk(pp) | | 2 | 4.5 | ns | note 2 | 13 |
| Output rise time tr (5V) | tr | | 2.5 | 4 | ns | 图 8-1 | 13 |
| Output fall time tf (5V) | tf | | 2.5 | 4 | ns | 图 8-1 | 13 |
| Default output delay time tDO (5V) | tDO | | 8 | 12 | ns | 图 8-2 | 13 |
| Start-up time tSU (5V) | tSU | | 15 | 40 | µs | | 13 |
| Supply current IDDA, DC signal (5V, H variant) | IDDA | | 2.9 | 4.4 | mA | DC signal; VIN = VDDI1 (CA-IS3763H) | 10 |
| Supply current IDDB, DC signal (5V, H variant) | IDDB | | 2.9 | 4.4 | mA | DC signal; VIN = VDDI1 (CA-IS3763H) | 10 |
| Supply current IDDA, DC signal (5V, H variant) | IDDA | | 5.5 | 8.4 | mA | DC signal; VIN = 0V (CA-IS3763H) | 10 |
| Supply current IDDB, DC signal (5V, H variant) | IDDB | | 5.5 | 8.4 | mA | DC signal; VIN = 0V (CA-IS3763H) | 10 |
| Supply current IDDA, AC signal (5V, H variant) | IDDA | | 4.3 | 6.5 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 1Mbps (500kHz) | 10 |
| Supply current IDDB, AC signal (5V, H variant) | IDDB | | 4.3 | 6.5 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 1Mbps (500kHz) | 10 |
| Supply current IDDA, AC signal (5V, H variant) | IDDA | | 5.7 | 8.4 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 10Mbps (5MHz) | 10 |
| Supply current IDDB, AC signal (5V, H variant) | IDDB | | 5.7 | 8.4 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 10Mbps (5MHz) | 10 |
| Supply current IDDA, AC signal (5V, H variant) | IDDA | | 19.9 | 30 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 100Mbps (50MHz) | 10 |
| Supply current IDDB, AC signal (5V, H variant) | IDDB | | 19.9 | 30 | mA | All channels 50% duty square wave, 5V amplitude; CL = 15 pF; 100Mbps (50MHz) | 10 |
| Thermal resistance junction-to-ambient RθJA | RθJA | | 110 | | °C/W | | 5 |
| High-level output voltage VOH (5V) | VOH | | 4.8 | | V | IOH = -4mA; 图 8-1 | 9 |
| Output impedance ZO (5V) | ZO | | 50 | | Ω | | 9 |
| Input capacitance CI (5V) | CI | | 2 | | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 9 |
## CAD (KiCad official)
- Symbol: `CA-IS3763HB`
- Footprint: `Package_SO:SSOP-16_5.3x6.2mm_P0.65mm`
- 3D model: SSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ca-is3763hb-etched.step` / `ca-is3763hb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is3763hb.step` / `ca-is3763hb.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590902618804215808) (22 pp, sha256 `0d88c3748184ff45`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ca-is3763hb-datasheet.pdf)