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CA-IS3762HN

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Chipanalog Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CA-IS3762HN

Chipanalog · Digital Isolators · SOIC-16

CA-IS3762HN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage, specified at 2.375 V to 5.5 V recommended operating range, with a 0.1 µF bypass capacitor placed within 2 mm of the pin.
2 VI1 input Side A logic input for forward channel 1, with Schmitt-trigger input and VIH/VIL thresholds of 2.0 V and 0.8 V.
3 VI2 input Side A logic input for forward channel 2, with Schmitt-trigger input and VIH/VIL thresholds of 2.0 V and 0.8 V.
4 VI3 input Side A logic input for forward channel 3, with Schmitt-trigger input and VIH/VIL thresholds of 2.0 V and 0.8 V.
5 VI4 input Side A logic input for forward channel 4 on CA-IS3762 (the pin is an output VO4 only on CA-IS3763), with Schmitt-trigger input and VIH/VIL thresholds of 2.0 V and 0.8 V.
6 VO5 output Side A logic output for reverse channel 5 on CA-IS3762, with 50 Ω typical output impedance and rail-to-rail swing.
7 VO6 output Side A logic output for reverse channel 6 on CA-IS3762, with 50 Ω typical output impedance and rail-to-rail swing.
8 GNDA power_in Side A ground reference point, which is the local ground for all Side A signals and supply.
9 GNDB power_in Side B ground reference point, which is the isolated local ground for Side B signals and supply.
10 VI6 input Side B logic input for reverse channel 6 on CA-IS3762, with Schmitt-trigger input and VIH/VIL thresholds of 2.0 V and 0.8 V.
11 VI5 input Side B logic input for reverse channel 5 on CA-IS3762, with Schmitt-trigger input and VIH/VIL thresholds of 2.0 V and 0.8 V.
12 VO4 output Side B logic output for forward channel 4 on CA-IS3762, with 50 Ω typical output impedance and rail-to-rail swing.
13 VO3 output Side B logic output for forward channel 3, with 50 Ω typical output impedance and rail-to-rail swing.
14 VO2 output Side B logic output for forward channel 2, with 50 Ω typical output impedance and rail-to-rail swing.
15 VO1 output Side B logic output for forward channel 1, with 50 Ω typical output impedance and rail-to-rail swing.
16 VDDB power_in Side B supply voltage, specified at 2.375 V to 5.5 V recommended operating range, with a 0.1 µF bypass capacitor placed within 2 mm of the pin.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB 2.375 3.3 5.5 V 5
VDD undervoltage threshold, rising supply VDD(UVLO+) 1.95 2.24 2.375 V 5
VDD undervoltage threshold, falling supply VDD(UVLO-) 1.88 2.1 2.325 V 5
VDD undervoltage hysteresis VHYS(UVLO) 70 140 250 mV 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signal data rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Supply voltage VDDA, VDDB absolute maximum VDDA, VDDB -0.5 6 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature range TSTG -65 150 °C 5
Positive input threshold, 5 V VIT+(IN) 1.4 1.67 1.9 V VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C 9
Negative input threshold, 5 V VIT-(IN) 1 1.23 1.4 V VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C 9
Input threshold hysteresis, 5 V VI(HYS) 0.3 0.44 0.5 V VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C 9
Output voltage logic low, 5 V VOL 0.2 0.4 V IOL = 4mA; 图 8-1 9
Common-mode transient immunity, 5 V CMTI 75 100 kV/µs VI = VDDI or 0 V, VCM = 1200 V; 图 8-3 9
Positive input threshold, 3.3 V VIT+(IN) 1.4 1.67 1.9 V VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C 9
Negative input threshold, 3.3 V VIT-(IN) 1 1.23 1.4 V VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C 9
Input threshold hysteresis, 3.3 V VI(HYS) 0.3 0.44 0.5 V VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C 9
Output voltage logic low, 3.3 V VOL 0.2 0.4 V IOL = 4mA; 图 8-1 9
Common-mode transient immunity, 3.3 V CMTI 75 100 kV/µs VI = VDDI or 0 V, VCM = 1200 V; 图 8-3 9
Positive input threshold, 2.5 V VIT+(IN) 1.4 1.67 1.9 V VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C 9
Negative input threshold, 2.5 V VIT-(IN) 1 1.23 1.4 V VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C 9
Input threshold hysteresis, 2.5 V VI(HYS) 0.3 0.44 0.5 V VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C 9
Output voltage logic low, 2.5 V VOL 0.2 0.4 V IOL = 4mA; 图 8-1 9
Common-mode transient immunity, 2.5 V CMTI 75 100 kV/µs VI = VDDI or 0 V, VCM = 1200 V; 图 8-3 9
Minimum pulse width, 5 V PWmin 5 ns 13
Propagation delay, 5 V tPLH, tPHL 5 8 13 ns 图 8-1 13
Pulse width distortion, 5 V PWD 0.2 4.5 ns /tPLH - tPHL/ 13
Channel-to-channel output skew, 5 V tsk(o) 0.4 2.5 ns 同方向通道 13
Part-to-part skew, 5 V tsk(pp) 2 4.5 ns 13
Output rise time, 5 V tr 2.5 4 ns 图 8-1 13
Output fall time, 5 V tf 2.5 4 ns 图 8-1 13
Default output delay from input power loss, 5 V tDO 8 12 ns 图 8-2 13
Startup time, 5 V tSU 15 40 µs 13
Minimum pulse width, 3.3 V PWmin 5 ns 13
Propagation delay, 3.3 V tPLH, tPHL 5 8 13 ns 图 8-1 13
Pulse width distortion, 3.3 V PWD 0.2 4.5 ns /tPLH - tPHL/ 13
Channel-to-channel output skew, 3.3 V tsk(o) 0.4 2.5 ns 同方向通道 13
Part-to-part skew, 3.3 V tsk(pp) 2 4.5 ns 13
Output rise time, 3.3 V tr 2.5 4 ns 图 8-1 13
Output fall time, 3.3 V tf 2.5 4 ns 图 8-1 13
Default output delay from input power loss, 3.3 V tDO 8 12 ns 图 8-2 13
Startup time, 3.3 V tSU 15 40 µs 13
Minimum pulse width, 2.5 V PWmin 5 ns 13
Propagation delay, 2.5 V tPLH, tPHL 5 8 13 ns 图 8-1 13
Pulse width distortion, 2.5 V PWD 0.2 5 ns /tPLH - tPHL/ 13
Channel-to-channel output skew, 2.5 V tsk(o) 0.4 2.5 ns 同方向通道 13
Part-to-part skew, 2.5 V tsk(pp) 2 5 ns 13
Output rise time, 2.5 V tr 2.5 4 ns 图 8-1 13
Output fall time, 2.5 V tf 2.5 4 ns 图 8-1 13
Default output delay from input power loss, 2.5 V tDO 8 12 ns 图 8-2 13
Startup time, 2.5 V tSU 15 40 µs 13
Thermal resistance junction-to-ambient, N (SOIC-16) RθJA 137.7 °C/W 6
Thermal resistance junction-to-case top, N (SOIC-16) RθJC(top) 54.9 °C/W 6
Thermal resistance junction-to-board, N (SOIC-16) RθJB 71.7 °C/W 6
Junction-to-top characterization parameter, N (SOIC-16) ψJT 7.1 °C/W 6
Junction-to-board characterization parameter, N (SOIC-16) ψJB 70.7 °C/W 6

CAD (KiCad official)

  • Symbol: CA-IS3762HN
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ca-is3762hn-etched.step / ca-is3762hn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3762hn.step / ca-is3762hn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 23308843cfcf0178, retrieved 2026-11-02, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF