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CA-IS3762HB

Public Made by Adom

by adom

Chipanalog Digital Isolators, SSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3762HB

Chipanalog · Digital Isolators · SSOP-16

CA-IS3762HB from Chipanalog, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage, recommended 2.375 V to 5.5 V, with a 0.1 µF to 1 µF bypass capacitor to GNDA.
2 VI1 input Side A logic input for channel 1, isolated to output VO1 on pin 15.
3 VI2 input Side A logic input for channel 2, isolated to output VO2 on pin 14.
4 VI3 input Side A logic input for channel 3, isolated to output VO3 on pin 13.
5 VI4 input Side A logic input for channel 4, isolated to output VO4 on pin 12.
6 VO5 output Side A logic output for reverse channel 5, driven from input VI5 on pin 11.
7 VO6 output Side A logic output for reverse channel 6, driven from input VI6 on pin 10.
8 GNDA power_in Side A ground reference.
9 GNDB power_in Side B ground reference.
10 VI6 input Side B logic input for reverse channel 6, isolated to output VO6 on pin 7.
11 VI5 input Side B logic input for reverse channel 5, isolated to output VO5 on pin 6.
12 VO4 output Side B logic output for channel 4, driven from input VI4 on pin 5.
13 VO3 output Side B logic output for channel 3, driven from input VI3 on pin 4.
14 VO2 output Side B logic output for channel 2, driven from input VI2 on pin 3.
15 VO1 output Side B logic output for channel 1, driven from input VI1 on pin 2.
16 VDDB power_in Side B supply voltage, recommended 2.375 V to 5.5 V, with a 0.1 µF to 1 µF bypass capacitor to GNDB.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SSOP-16
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB 2.375 5.5 V typ 3.3/5.0 5
Ambient temperature TA -40 27 125 °C 5
Data rate DR 0 150 Mbps 5
High-level input threshold VIH 2 V 5
Low-level input threshold VIL 0.8 V 5
High-level output current IOH -4 mA VDDO = 5V 5
Low-level output current IOL 4 mA VDDO = 5V 5
UVLO rising threshold VDD(UVLO+) 1.95 2.24 2.375 V 5
UVLO falling threshold VDD(UVLO-) 1.88 2.1 2.325 V 5
UVLO hysteresis VHYS(UVLO) 70 140 250 mV 5
Supply voltage VDDA, VDDB -0.5 7 V 5
Input voltage Vin -0.5 V max VDD+0.5, not to exceed 7 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature TSTG -65 150 °C 5
ESD HBM VESD -6000 6000 V ANSI/ESDA/JEDEC JS-001, all pins 5
ESD CDM VESD -2000 2000 V JESD22-C101, all pins 5
Junction-to-ambient thermal resistance RθJA 110 °C/W SSOP16(B) 5
Maximum power dissipation PD 494 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave 6
Side A max power dissipation PDA 180 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave 6
Side B max power dissipation PDB 314 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave 6
High-level output voltage VOH 4.8 V IOH = -4mA; VDD 5V±10%; min printed VDDO-0.4 9
Low-level output voltage VOL 0.2 0.4 V IOL = 4mA; VDD 5V±10% 9
Input threshold high VIT+(IN) 2 V 9
Input threshold low VIT-(IN) 0.8 V 9
High-level input leakage current IIH 20 µA VIH = VDDA at Ax or Bx 9
Low-level input leakage current IIL -20 µA VIL = 0 V at Ax or Bx 9
Output impedance ZO 50 Ω 9
Common-mode transient immunity CMTI 50 kV/µs VI = VDDI or 0 V, VCM = 1200 V 9
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V 9
IDDA DC, VIN=0V (H) IDDA 2.8 4.5 mA VDD 5V±10%; VIN = VDDI (CA-IS3762L); VIN = 0V (CA-IS3762H)... first row VIN=0V(L)/VDDI(H) 10
IDDB DC, VIN=0V (H) IDDB 3.8 5.8 mA VDD 5V±10%; first DC row 10
IDDA DC, VIN=0V IDDA 6.2 9.9 mA VDD 5V±10%; VIN = 0V (CA-IS3762H) 10
IDDB DC, VIN=0V IDDB 5.6 8.7 mA VDD 5V±10%; VIN = 0V (CA-IS3762H) 10
IDDA 1Mbps IDDA 5.4 8.3 mA 5V square wave, CL = 15 pF, 1Mbps (500kHz) 10
IDDB 1Mbps IDDB 6.3 9.5 mA 5V square wave, CL = 15 pF, 1Mbps (500kHz) 10
IDDA 10Mbps IDDA 13.1 18.3 mA 5V square wave, CL = 15 pF, 10Mbps (5MHz) 10
IDDB 10Mbps IDDB 21 31.5 mA 5V square wave, CL = 15 pF, 10Mbps (5MHz) 10
IDDA 100Mbps IDDA 26 36.9 mA 5V square wave, CL = 15 pF, 100Mbps (50MHz) 10
IDDB 100Mbps IDDB 44.7 72.2 mA 5V square wave, CL = 15 pF, 100Mbps (50MHz) 10
Data rate DR 0 150 Mbps VDD 5V±10% 13
Minimum pulse width PWmin 5 ns 13
Propagation delay tPLH, tPHL 5 12 15 ns Figure 8-1 13
Pulse width distortion PWD 0.2 4.5 ns /tPLH - tPHL/ 13
Channel-to-channel output skew tsk(o) 0.4 2.5 ns same-direction channels 13
Part-to-part skew tsk(pp) 2 4.5 ns 13
Output rise time tr 2.5 4 ns Figure 8-1 13
Output fall time tf 2.5 4 ns Figure 8-1 13
Default output delay time tDO 8 12 ns Figure 8-2 13
Start-up time tSU 15 40 µs 13

CAD (KiCad official)

  • Symbol: CA-IS3762HB
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ca-is3762hb-etched.step / ca-is3762hb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3762hb.step / ca-is3762hb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 01dcf402a9677bc8, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF