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CA-IS3761LB

Public Made by Adom

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Chipanalog Digital Isolators, SSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentisolatorsca-is3761lbfactory-2.0.0extractor-text

Verified CA-IS3761LB

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CA-IS3761LB · SSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 22-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SSOP-16_5.3x6.2mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-4uk4l3oh/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ca-is3761lb.kicad_sym✓ ca-is3761lb.kicad_mod✓ ca-is3761lb.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers ca-is3761lb: viewers · Ray
ca-is3761lb-etched.glb Publish 0.1.0 · Ray
ca-is3761lb-etched.step ca-is3761lb: factory component page (tier=lcsc) · Ray
ca-is3761lb-hero.glb ca-is3761lb: hero GLB from the etched model (keeps the MPN mark) · Ray
ca-is3761lb-hero.overlay.json Publish 0.1.0 · Ray
ca-is3761lb.glb Publish 0.1.0 · Ray
ca-is3761lb.kicad_mod Publish 0.1.0 · Ray
ca-is3761lb.kicad_sym Publish 0.1.0 · Ray
ca-is3761lb.lbr Publish 0.1.0 · Ray
ca-is3761lb.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 16 pins · Ray

CA-IS3761LB

Chipanalog · Digital Isolators · SSOP-16

CA-IS3761LB from Chipanalog, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side-A supply voltage, recommended 2.375 V to 5.5 V (typ. 3.3/5.0 V); absolute maximum 7.0 V relative to GNDA.
2 VI1 input Side-A logic input, channel 1 (forward, A to B); Schmitt-trigger input with VIH min 2.0 V and VIL max 0.8 V.
3 VI2 input Side-A logic input, channel 2 (forward, A to B); Schmitt-trigger input with VIH min 2.0 V and VIL max 0.8 V.
4 VI3 input Side-A logic input, channel 3 (forward, A to B); Schmitt-trigger input with VIH min 2.0 V and VIL max 0.8 V.
5 VI4 input Side-A logic input, channel 4 (forward, A to B); Schmitt-trigger input with VIH min 2.0 V and VIL max 0.8 V.
6 VI5 input Side-A logic input, channel 5 (forward, A to B); Schmitt-trigger input with VIH min 2.0 V and VIL max 0.8 V.
7 VO6 output Side-A logic output of reverse channel 6 (driven from B-side input VI6); default output is low for L-suffix devices and high for H-suffix devices when the input-side supply is lost.
8 GNDA power_in Side-A ground reference for the isolated A-side circuitry.
9 GNDB power_in Side-B isolated ground reference for the B-side circuitry.
10 VI6 input Side-B logic input of reverse channel 6 (B to A); Schmitt-trigger input with VIH min 2.0 V and VIL max 0.8 V.
11 VO5 output Side-B logic output of forward channel 5 (A to B); drives up to 4 mA high-level/low-level at 5 V per recommended operating conditions (IOH -4 mA, IOL 4 mA at VDDO = 5 V).
12 VO4 output Side-B logic output of forward channel 4 (A to B); drives up to 4 mA at 5 V per recommended operating conditions (IOH -4 mA, IOL 4 mA at VDDO = 5 V).
13 VO3 output Side-B logic output of forward channel 3 (A to B); drives up to 4 mA at 5 V per recommended operating conditions (IOH -4 mA, IOL 4 mA at VDDO = 5 V).
14 VO2 output Side-B logic output of forward channel 2 (A to B); drives up to 4 mA at 5 V per recommended operating conditions (IOH -4 mA, IOL 4 mA at VDDO = 5 V).
15 VO1 output Side-B logic output of forward channel 1 (A to B); drives up to 4 mA at 5 V per recommended operating conditions (IOH -4 mA, IOL 4 mA at VDDO = 5 V).
16 VDDB power_in Side-B supply voltage, recommended 2.375 V to 5.5 V (typ. 3.3/5.0 V); absolute maximum 7.0 V relative to GNDB.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SSOP-16
Category Isolators
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB 2.375 5.5 V Recommended operating; typ printed as 3.3/5.0 5
VDD undervoltage threshold, rising VDD（UVLO+） 1.95 2.24 2.375 V VDD rising 5
VDD undervoltage threshold, falling VDD（UVLO-） 1.88 2.1 2.325 V VDD falling 5
VDD undervoltage hysteresis VHYS（UVLO） 70 140 250 mV VDD UVLO hysteresis 5
High-level output current IOH -4 mA VDDO1 = 5V 5
High-level output current IOH -2 mA VDDO = 3.3V 5
High-level output current IOH -1 mA VDDO = 2.5V 5
Low-level output current IOL 4 mA VDDO = 5V 5
Low-level output current IOL 2 mA VDDO = 3.3V 5
Low-level output current IOL 1 mA VDDO = 2.5V 5
Input threshold logic-high VIH 2 V 5
Input threshold logic-low VIL 0.8 V 5
Signaling data rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Supply voltage VDDA, VDDB VDDA, VDDB -0.5 7 V Relative to local ground (GNDA or GNDB), peak value 5
Input voltage Ax, Bx Vin -0.5 V Max printed as VDD+0.5 (expression, not computed); relative to local ground 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature range TSTG -65 150 °C 5
Low-level output voltage VOL 0.2 0.4 V IOL = 4mA; Fig 8-1; VDDA = VDDB = 5 V ±10% 9
Input threshold logic-high VIT+(IN) 2 V VDDA = VDDB = 5 V ±10% 9
Input threshold logic-low VIT-(IN) 0.8 V VDDA = VDDB = 5 V ±10% 9
Input high-level leakage current IIH 20 µA VIH = VDDA at Ax or Bx 9
Input low-level leakage current IIL -20 µA VIL = 0 V at Ax or Bx 9
Common-mode transient immunity CMTI 50 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; Fig 8-3 9
Supply current, DC input, VDDA (L) IDDA 2.3 3.4 mA VDDA = VDDB = 5 V ±10%; VIN = 0V (CA-IS3761L); DC signal 10
Supply current, DC input, VDDB (L) IDDB 3.6 5.3 mA VDDA = VDDB = 5 V ±10%; VIN = 0V (CA-IS3761L); DC signal 10
Supply current, AC, VDDA, 1 Mbps IDDA 4.5 6.7 mA All channel inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 1 Mbps (500 kHz) 10
Supply current, AC, VDDB, 1 Mbps IDDB 5.7 8.4 mA All channel inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 1 Mbps (500 kHz) 10
Supply current, AC, VDDA, 10 Mbps IDDA 5.1 7.6 mA All channel inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 10 Mbps (5 MHz) 10
Supply current, AC, VDDB, 10 Mbps IDDB 19.8 29.9 mA All channel inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 10 Mbps (5 MHz) 10
Supply current, AC, VDDA, 100 Mbps IDDA 10.6 16.3 mA All channel inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 100 Mbps (50 MHz) 10
Supply current, AC, VDDB, 100 Mbps IDDB 45.6 62.1 mA All channel inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 100 Mbps (50 MHz) 10
Minimum pulse width PWmin 5 ns VDDA = VDDB = 5 V ±10% 13
Propagation delay tPLH, tPHL 5 12 15 ns Fig 8-1; VDDA = VDDB = 5 V ±10% 13
Pulse width distortion PWD 0.2 4.5 ns /tPLH − tPHL/; VDDA = VDDB = 5 V ±10% 13
Channel-to-channel output skew tsk(o) 0.4 2.5 ns Same-direction channels; VDDA = VDDB = 5 V ±10% 13
Part-to-part output skew tsk(pp) 2 4.5 ns VDDA = VDDB = 5 V ±10% 13
Output rise time tr 2.5 4 ns Fig 8-1; VDDA = VDDB = 5 V ±10% 13
Output fall time tf 2.5 4 ns Fig 8-1; VDDA = VDDB = 5 V ±10% 13
Default output delay time from input power loss tDO 8 12 ns Fig 8-2; VDDA = VDDB = 5 V ±10% 13
Startup time tSU 15 40 µs VDDA = VDDB = 5 V ±10% 13
High-level output voltage VOH 4.8 V IOH = -4mA; Fig 8-1; VDDA = VDDB = 5 V ±10%; min printed as VDDO1-0.4 (expression) 9
Output impedance ZO 50 Ω VDDA = VDDB = 5 V ±10% 9
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V 9
Junction-to-ambient thermal resistance RθJA 110 °C/W SSOP16(B) package 5

CAD (KiCad official)

  • Symbol: CA-IS3761LB
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ca-is3761lb-etched.step / ca-is3761lb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3761lb.step / ca-is3761lb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 0d88c3748184ff45, retrieved 2026-10-30, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF