component
CA-IS3761HW
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CA-IS3761HW
Chipanalog · Digital Isolators · SOIC-16-300mil
CA-IS3761HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side supply voltage, recommended 2.375 V to 5.5 V with an absolute maximum of 6.0 V, referenced to GNDA. |
| 2 | VI1 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 3 | VI2 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 4 | VI3 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 5 | VI4 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 6 | VI5 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 7 | VO6 | output | A-side reverse-channel logic output, rail-to-rail with about 50 Ω output impedance; it takes the default-high state (CA-IS376xH) when the input-side supply is lost. |
| 8 | GNDA | power_in | A-side ground reference point; all voltages on the A side are referenced to this pin. |
| 9 | GNDB | power_in | B-side ground reference point; all voltages on the B side are referenced to this pin. |
| 10 | VI6 | input | B-side reverse-channel logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 11 | VO5 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 12 | VO4 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 13 | VO3 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 14 | VO2 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 15 | VO1 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 16 | VDDB | power_in | B-side supply voltage, recommended 2.375 V to 5.5 V with an absolute maximum of 6.0 V, referenced to GNDB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 (VDDA, VDDB) | VDDA, VDDB | -0.5 | 6 | V | 5 | ||
| 输入电压 | Vin | -0.5 | V | Ax, Bx, ENx | 5 | ||
| 输出电流 | IO | -20 | 20 | mA | 5 | ||
| 结温 | TJ | 150 | °C | 5 | |||
| 存储温度范围 | TSTG | -65 | 150 | °C | 5 | ||
| 电源电压 (VDDA, VDDB) | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | 5 | |
| VDD 电源电压上升时的欠压阈值 | VDD（UVLO+） | 1.95 | 2.24 | 2.375 | V | 5 | |
| VDD 电源电压下降时的欠压阈值 | VDD（UVLO-） | 1.88 | 2.1 | 2.325 | V | 5 | |
| VDD 迟滞欠压阈值 | VHYS（UVLO） | 70 | 140 | 250 | mV | 5 | |
| 高电平输出电流 | IOH | -4 | mA | VDDO = 5V | 5 | ||
| 高电平输出电流 | IOH | -2 | mA | VDDO = 3.3V | 5 | ||
| 高电平输出电流 | IOH | -1 | mA | VDDO = 2.5V | 5 | ||
| 低电平输出电流 | IOL | 4 | mA | VDDO = 5V | 5 | ||
| 低电平输出电流 | IOL | 2 | mA | VDDO = 3.3V | 5 | ||
| 低电平输出电流 | IOL | 1 | mA | VDDO = 2.5V | 5 | ||
| 输入阈值逻辑高电平 | VIH | 2 | V | 5 | |||
| 输入阈值逻辑低电平 | VIL | 0.8 | V | 5 | |||
| 信号传输速率 | DR | 0 | 150 | Mbps | 5 | ||
| 环境温度 | TA | -40 | 27 | 125 | °C | 5 | |
| 输出电压逻辑低电平 | VOL | 0.2 | 0.4 | V | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C; IOL = 4mA; 图 7-1 | 9 | |
| 正输入阈值 | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C | 9 |
| 负输入阈值 | VIT-(IN) | 1 | 1.23 | 1.4 | V | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C | 9 |
| 输入阈值迟滞 | VI(HYS) | 0.3 | 0.44 | 0.5 | V | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C | 9 |
| 输入高电平漏电流 | IIH | 4 | µA | VDDA=VDDB=5 V ±10%; VIH = VDDA at Ax or Bx or ENx | 9 | ||
| 输入低电平漏电流 | IIL | -4 | µA | VDDA=VDDB=5 V ±10%; VIL = 0 V at Ax or Bx | 9 | ||
| 共模瞬变抗扰度 | CMTI | 75 | 100 | kV/µs | VDDA=VDDB=5 V ±10%; VI = VDDI1 or 0 V, VCM = 1200 V; 图 7-3 | 9 | |
| 最小脉宽 | PWmin | 5 | ns | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C | 13 | ||
| 传播延迟 | tPLH, tPHL | 5 | 8 | 13 | ns | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C; 图 7-1 | 13 |
| 脉冲宽度失真 | PWD | 0.2 | 4.5 | ns | VDDA=VDDB=5 V ±10%; /tPLH - tPHL/ | 13 | |
| 输出上升时间 | tr | 2.5 | 4 | ns | VDDA=VDDB=5 V ±10%; 图 7-1 | 13 | |
| 输出下降时间 | tf | 2.5 | 4 | ns | VDDA=VDDB=5 V ±10%; 图 7-1 | 13 | |
| 默认输出延迟时间从输入电源损耗 | tDO | 8 | 12 | ns | VDDA=VDDB=5 V ±10%; 图 7-2 | 13 | |
| 启动时间 | tSU | 15 | 40 | µs | VDDA=VDDB=5 V ±10% | 13 | |
| 电源电流 DC（A侧，H版本） | IDDA | 1.9 | 2.9 | mA | VDDA=VDDB=5 V ±10%; DC signal; VIN = VDDI1 (CA-IS3761H) | 10 | |
| 电源电流 DC（B侧，H版本） | IDDB | 2.9 | 5.9 | mA | VDDA=VDDB=5 V ±10%; DC signal; VIN = VDDI1 (CA-IS3761H) | 10 | |
| 电源电流 DC（A侧，H版本，输入0V） | IDDA | 5.7 | 8.5 | mA | VDDA=VDDB=5 V ±10%; DC signal; VIN = 0V (CA-IS3761H) | 10 | |
| 电源电流 DC（B侧，H版本，输入0V） | IDDB | 4.9 | 7.3 | mA | VDDA=VDDB=5 V ±10%; DC signal; VIN = 0V (CA-IS3761H) | 10 | |
| 隔离电压 (UL 1577, W封装) | VISO | 5000 | VRMS | UL 1577; VTEST = VISO, t = 60 s (认证) | 7 | ||
| 输出电压逻辑高电平 | VOH | 4.8 | V | VDDA=VDDB=5 V ±10%; IOH = -4mA; 图 7-1 | 9 | ||
| 输出电压逻辑高电平 | VOH | 3.1 | V | VDDA=VDDB=3.3 V ±10%; IOH = -4mA; 图 7-1 | 9 | ||
| 输出电压逻辑高电平 | VOH | 2.3 | V | VDDA=VDDB=2.5 V ±5%; IOH = -4mA; 图 7-1 | 9 | ||
| 结到环境热阻 (SOIC16-WB) | RθJA | 83.4 | °C/W | W (SOIC16-WB) package | 6 | ||
| 结到壳(顶部)热阻 (SOIC16-WB) | RθJC(top) | 46 | °C/W | W (SOIC16-WB) package | 6 | ||
| 结到板热阻 (SOIC16-WB) | RθJB | 48 | °C/W | W (SOIC16-WB) package | 6 | ||
| 结到顶部表征参数 (SOIC16-WB) | ψJT | 19.1 | °C/W | W (SOIC16-WB) package | 6 | ||
| 结至板表征参数 (SOIC16-WB) | ψJB | 47.5 | °C/W | W (SOIC16-WB) package | 6 |
CAD (KiCad official)
- Symbol:
CA-IS3761HW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is3761hw-etched.step/ca-is3761hw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3761hw.step/ca-is3761hw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (22 pp, sha256
adf22151c4806ef6, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CA-IS3761HW
**Chipanalog** · Digital Isolators · SOIC-16-300mil
CA-IS3761HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side supply voltage, recommended 2.375 V to 5.5 V with an absolute maximum of 6.0 V, referenced to GNDA. |
| 2 | VI1 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 3 | VI2 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 4 | VI3 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 5 | VI4 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 6 | VI5 | input | A-side forward logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 7 | VO6 | output | A-side reverse-channel logic output, rail-to-rail with about 50 Ω output impedance; it takes the default-high state (CA-IS376xH) when the input-side supply is lost. |
| 8 | GNDA | power_in | A-side ground reference point; all voltages on the A side are referenced to this pin. |
| 9 | GNDB | power_in | B-side ground reference point; all voltages on the B side are referenced to this pin. |
| 10 | VI6 | input | B-side reverse-channel logic input with Schmitt-trigger thresholds, VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 11 | VO5 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 12 | VO4 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 13 | VO3 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 14 | VO2 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 15 | VO1 | output | B-side forward-channel logic output, rail-to-rail with about 50 Ω output impedance. |
| 16 | VDDB | power_in | B-side supply voltage, recommended 2.375 V to 5.5 V with an absolute maximum of 6.0 V, referenced to GNDB. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 电源电压 (VDDA, VDDB) | VDDA, VDDB | -0.5 | | 6 | V | | 5 |
| 输入电压 | Vin | -0.5 | | | V | Ax, Bx, ENx | 5 |
| 输出电流 | IO | -20 | | 20 | mA | | 5 |
| 结温 | TJ | | | 150 | °C | | 5 |
| 存储温度范围 | TSTG | -65 | | 150 | °C | | 5 |
| 电源电压 (VDDA, VDDB) | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | | 5 |
| VDD 电源电压上升时的欠压阈值 | VDD（UVLO+） | 1.95 | 2.24 | 2.375 | V | | 5 |
| VDD 电源电压下降时的欠压阈值 | VDD（UVLO-） | 1.88 | 2.1 | 2.325 | V | | 5 |
| VDD 迟滞欠压阈值 | VHYS（UVLO） | 70 | 140 | 250 | mV | | 5 |
| 高电平输出电流 | IOH | -4 | | | mA | VDDO = 5V | 5 |
| 高电平输出电流 | IOH | -2 | | | mA | VDDO = 3.3V | 5 |
| 高电平输出电流 | IOH | -1 | | | mA | VDDO = 2.5V | 5 |
| 低电平输出电流 | IOL | | | 4 | mA | VDDO = 5V | 5 |
| 低电平输出电流 | IOL | | | 2 | mA | VDDO = 3.3V | 5 |
| 低电平输出电流 | IOL | | | 1 | mA | VDDO = 2.5V | 5 |
| 输入阈值逻辑高电平 | VIH | 2 | | | V | | 5 |
| 输入阈值逻辑低电平 | VIL | | | 0.8 | V | | 5 |
| 信号传输速率 | DR | 0 | | 150 | Mbps | | 5 |
| 环境温度 | TA | -40 | 27 | 125 | °C | | 5 |
| 输出电压逻辑低电平 | VOL | | 0.2 | 0.4 | V | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C; IOL = 4mA; 图 7-1 | 9 |
| 正输入阈值 | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C | 9 |
| 负输入阈值 | VIT-(IN) | 1 | 1.23 | 1.4 | V | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C | 9 |
| 输入阈值迟滞 | VI(HYS) | 0.3 | 0.44 | 0.5 | V | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C | 9 |
| 输入高电平漏电流 | IIH | | | 4 | µA | VDDA=VDDB=5 V ±10%; VIH = VDDA at Ax or Bx or ENx | 9 |
| 输入低电平漏电流 | IIL | -4 | | | µA | VDDA=VDDB=5 V ±10%; VIL = 0 V at Ax or Bx | 9 |
| 共模瞬变抗扰度 | CMTI | 75 | 100 | | kV/µs | VDDA=VDDB=5 V ±10%; VI = VDDI1 or 0 V, VCM = 1200 V; 图 7-3 | 9 |
| 最小脉宽 | PWmin | 5 | | | ns | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C | 13 |
| 传播延迟 | tPLH, tPHL | 5 | 8 | 13 | ns | VDDA=VDDB=5 V ±10%, TA=-40 to 125°C; 图 7-1 | 13 |
| 脉冲宽度失真 | PWD | 0.2 | | 4.5 | ns | VDDA=VDDB=5 V ±10%; /tPLH - tPHL/ | 13 |
| 输出上升时间 | tr | 2.5 | | 4 | ns | VDDA=VDDB=5 V ±10%; 图 7-1 | 13 |
| 输出下降时间 | tf | 2.5 | | 4 | ns | VDDA=VDDB=5 V ±10%; 图 7-1 | 13 |
| 默认输出延迟时间从输入电源损耗 | tDO | 8 | | 12 | ns | VDDA=VDDB=5 V ±10%; 图 7-2 | 13 |
| 启动时间 | tSU | 15 | | 40 | µs | VDDA=VDDB=5 V ±10% | 13 |
| 电源电流 DC（A侧，H版本） | IDDA | 1.9 | | 2.9 | mA | VDDA=VDDB=5 V ±10%; DC signal; VIN = VDDI1 (CA-IS3761H) | 10 |
| 电源电流 DC（B侧，H版本） | IDDB | 2.9 | | 5.9 | mA | VDDA=VDDB=5 V ±10%; DC signal; VIN = VDDI1 (CA-IS3761H) | 10 |
| 电源电流 DC（A侧，H版本，输入0V） | IDDA | 5.7 | | 8.5 | mA | VDDA=VDDB=5 V ±10%; DC signal; VIN = 0V (CA-IS3761H) | 10 |
| 电源电流 DC（B侧，H版本，输入0V） | IDDB | 4.9 | | 7.3 | mA | VDDA=VDDB=5 V ±10%; DC signal; VIN = 0V (CA-IS3761H) | 10 |
| 隔离电压 (UL 1577, W封装) | VISO | | | 5000 | VRMS | UL 1577; VTEST = VISO, t = 60 s (认证) | 7 |
| 输出电压逻辑高电平 | VOH | | 4.8 | | V | VDDA=VDDB=5 V ±10%; IOH = -4mA; 图 7-1 | 9 |
| 输出电压逻辑高电平 | VOH | | 3.1 | | V | VDDA=VDDB=3.3 V ±10%; IOH = -4mA; 图 7-1 | 9 |
| 输出电压逻辑高电平 | VOH | | 2.3 | | V | VDDA=VDDB=2.5 V ±5%; IOH = -4mA; 图 7-1 | 9 |
| 结到环境热阻 (SOIC16-WB) | RθJA | | 83.4 | | °C/W | W (SOIC16-WB) package | 6 |
| 结到壳(顶部)热阻 (SOIC16-WB) | RθJC(top) | | 46 | | °C/W | W (SOIC16-WB) package | 6 |
| 结到板热阻 (SOIC16-WB) | RθJB | | 48 | | °C/W | W (SOIC16-WB) package | 6 |
| 结到顶部表征参数 (SOIC16-WB) | ψJT | | 19.1 | | °C/W | W (SOIC16-WB) package | 6 |
| 结至板表征参数 (SOIC16-WB) | ψJB | | 47.5 | | °C/W | W (SOIC16-WB) package | 6 |
## CAD (KiCad official)
- Symbol: `CA-IS3761HW`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `ca-is3761hw-etched.step` / `ca-is3761hw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is3761hw.step` / `ca-is3761hw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907953331691520) (22 pp, sha256 `adf22151c4806ef6`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ca-is3761hw-datasheet.pdf)