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CA-IS3761HB

Public Made by Adom

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Chipanalog Digital Isolators, SSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3761HB

Chipanalog · Digital Isolators · SSOP-16

CA-IS3761HB from Chipanalog, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in A-side supply voltage, operating range 2.375 V to 5.5 V (absolute maximum 7.0 V relative to GNDA).
2 VI1 input A-side logic input of channel 1 with Schmitt-trigger threshold: VIH minimum 2.0 V and VIL maximum 0.8 V.
3 VI2 input A-side logic input of channel 2 with Schmitt-trigger threshold: VIH minimum 2.0 V and VIL maximum 0.8 V.
4 VI3 input A-side logic input of channel 3 with Schmitt-trigger threshold: VIH minimum 2.0 V and VIL maximum 0.8 V.
5 VI4 input A-side logic input of channel 4 with Schmitt-trigger threshold: VIH minimum 2.0 V and VIL maximum 0.8 V.
6 VI5 input A-side logic input of channel 5 with Schmitt-trigger threshold: VIH minimum 2.0 V and VIL maximum 0.8 V.
7 VO6 output A-side logic output of the reverse channel 6, with output current limited to IOH -4 mA at 5 V (-2 mA at 3.3 V, -1 mA at 2.5 V) and IOL 4 mA at 5 V (2 mA at 3.3 V, 1 mA at 2.5 V).
8 GNDA power_in A-side ground reference point for the A-side supply and logic.
9 GNDB power_in B-side ground reference point, isolated from GNDA.
10 VI6 input B-side logic input of reverse channel 6 with Schmitt-trigger threshold: VIH minimum 2.0 V and VIL maximum 0.8 V.
11 VO5 output B-side logic output of channel 5, with output current limited to IOH -4 mA at 5 V and IOL 4 mA at 5 V (lower at 3.3 V and 2.5 V).
12 VO4 output B-side logic output of channel 4, with output current limited to IOH -4 mA at 5 V and IOL 4 mA at 5 V (lower at 3.3 V and 2.5 V).
13 VO3 output B-side logic output of channel 3, with output current limited to IOH -4 mA at 5 V and IOL 4 mA at 5 V (lower at 3.3 V and 2.5 V).
14 VO2 output B-side logic output of channel 2, with output current limited to IOH -4 mA at 5 V and IOL 4 mA at 5 V (lower at 3.3 V and 2.5 V).
15 VO1 output B-side logic output of channel 1, with output current limited to IOH -4 mA at 5 V and IOL 4 mA at 5 V (lower at 3.3 V and 2.5 V).
16 VDDB power_in B-side supply voltage, operating range 2.375 V to 5.5 V (absolute maximum 7.0 V relative to GNDB).

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SSOP-16
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB (absolute maximum) VDDA, VDDB -0.5 7 V Peak voltage relative to GNDA/GNDB 5
Input voltage Ax, Bx (absolute maximum) Vin -0.5 V Printed as VDD+0.5 (footnote 3: must not exceed 7 V); max not numeric 5
Output current (absolute maximum) IO -20 20 mA 5
Junction temperature (absolute maximum) TJ 150 °C 5
Storage temperature range (absolute maximum) TSTG -65 150 °C 5
ESD human body model VESD -6000 6000 V HBM, ANSI/ESDA/JEDEC JS-001, all pins; printed ±6000 5
ESD charged device model VESD -2000 2000 V CDM, JEDEC JESD22-C101, all pins; printed ±2000 5
Supply voltage VDDA, VDDB (recommended) VDDA, VDDB 2.375 5.5 V Typical printed as 3.3/5.0 (not a single value) 5
UVLO threshold, rising VDD(UVLO+) 1.95 2.24 2.375 V VDD rising 5
UVLO threshold, falling VDD(UVLO-) 1.88 2.1 2.325 V VDD falling 5
UVLO hysteresis VHYS(UVLO) 70 140 250 mV 5
High-level output current IOH -4 mA VDDO1 = 5 V 5
High-level output current IOH -2 mA VDDO = 3.3 V 5
High-level output current IOH -1 mA VDDO = 2.5 V 5
Low-level output current IOL 4 mA VDDO = 5 V 5
Low-level output current IOL 2 mA VDDO = 3.3 V 5
Low-level output current IOL 1 mA VDDO = 2.5 V 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signal data rate (recommended) DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Logic output voltage low VOL 0.2 0.4 V VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; IOL = 4 mA; Fig 8-1 9
Input threshold logic high VIT+(IN) 2 V VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C (same value printed in 7.8.2 and 7.8.3) 9
Input threshold logic low VIT-(IN) 0.8 V VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C (same value printed in 7.8.2 and 7.8.3) 9
Input high-level leakage current IIH 20 µA VDDA = VDDB = 5 V ± 10%; VIH = VDDA at Ax or Bx (same value printed in 7.8.2 and 7.8.3) 9
Input low-level leakage current IIL -20 µA VDDA = VDDB = 5 V ± 10%; VIL = 0 V at Ax or Bx (same value printed in 7.8.2 and 7.8.3) 9
Output impedance tolerance (normal isolator channel) ZO -40 40 % Footnote 2: normal isolator channel, printed as ~50 Ω ±40% 9
Common-mode transient immunity CMTI 50 kV/µs VDDA = VDDB = 5 V ± 10%; VI = VDDI1 or 0 V, VCM = 1200 V; Fig 8-3 (same value printed in 7.8.2 and 7.8.3) 9
Signal data rate (timing) DR 0 150 Mbps VDDA = VDDB = 5 V ± 10% 13
Minimum pulse width PWmin 5 ns VDDA = VDDB = 5 V ± 10% 13
Propagation delay tPLH, tPHL 5 12 15 ns VDDA = VDDB = 5 V ± 10%; Fig 8-1 13
Pulse width distortion PWD 0.2 4.5 ns VDDA = VDDB = 5 V ± 10%; /tPLH - tPHL/ 13
Channel-to-channel output skew, same direction tsk(o) 0.4 2.5 ns VDDA = VDDB = 5 V ± 10%; same-direction channels 13
Part-to-part output skew tsk(pp) 2 4.5 ns VDDA = VDDB = 5 V ± 10%; footnote 2 13
Part-to-part output skew tsk(pp) 1 5 ns VDDA = VDDB = 2.5 V ± 5%; footnote 2 13
Output rise time tr 2.5 4 ns VDDA = VDDB = 5 V ± 10%; Fig 8-1 13
Output fall time tf 2.5 4 ns VDDA = VDDB = 5 V ± 10%; Fig 8-1 13
Default output delay time from input power loss tDO 8 12 ns VDDA = VDDB = 5 V ± 10%; Fig 8-2 13
Startup time tSU 15 40 µs VDDA = VDDB = 5 V ± 10% 13
Supply current IDDA, DC, H variant IDDA 2.3 3.4 mA VDDA = VDDB = 5 V ± 10%; VIN = VDDI1 (CA-IS3761H), DC 10
Supply current IDDB, DC, H variant IDDB 3.6 5.3 mA VDDA = VDDB = 5 V ± 10%; VIN = VDDI1 (CA-IS3761H), DC 10
Supply current IDDA, DC, H variant IDDA 6.5 9.9 mA VDDA = VDDB = 5 V ± 10%; VIN = 0V (CA-IS3761H), DC 10
Supply current IDDB, DC, H variant IDDB 4.6 6.9 mA VDDA = VDDB = 5 V ± 10%; VIN = 0V (CA-IS3761H), DC 10
Supply current IDDA, DC, H variant IDDA 2.2 3.2 mA VDDA = VDDB = 3.3 V ± 10%; VIN = VDDI1 (CA-IS3761H), DC 11
Supply current IDDB, DC, H variant IDDB 3.4 5 mA VDDA = VDDB = 3.3 V ± 10%; VIN = VDDI1 (CA-IS3761H), DC 11
Supply current IDDA, DC, H variant IDDA 6.3 9.7 mA VDDA = VDDB = 3.3 V ± 10%; VIN = 0V (CA-IS3761H), DC 11
Supply current IDDB, DC, H variant IDDB 4.4 6.5 mA VDDA = VDDB = 3.3 V ± 10%; VIN = 0V (CA-IS3761H), DC 11
Supply current IDDA, DC, H variant IDDA 2.1 3.2 mA VDDA = VDDB = 2.5 V ± 5%; VIN = VDDI1 (CA-IS3761H), DC 12
Supply current IDDB, DC, H variant IDDB 3.3 4.8 mA VDDA = VDDB = 2.5 V ± 5%; VIN = VDDI1 (CA-IS3761H), DC 12
Supply current IDDA, DC, H variant IDDA 6.3 9.6 mA VDDA = VDDB = 2.5 V ± 5%; VIN = 0V (CA-IS3761H), DC 12
Supply current IDDB, DC, H variant IDDB 4.3 6.4 mA VDDA = VDDB = 2.5 V ± 5%; VIN = 0V (CA-IS3761H), DC 12
Supply current IDDA, switching 1 Mbps IDDA 4.5 6.7 mA VDDA = VDDB = 5 V ± 10%; all channels 50% duty square wave 5 V, CL = 15 pF, 1 Mbps (500 kHz) 10
Supply current IDDB, switching 1 Mbps IDDB 5.7 8.4 mA VDDA = VDDB = 5 V ± 10%; all channels 50% duty square wave 5 V, CL = 15 pF, 1 Mbps (500 kHz) 10
Supply current IDDA, switching 10 Mbps IDDA 5.1 7.6 mA VDDA = VDDB = 5 V ± 10%; all channels 50% duty square wave 5 V, CL = 15 pF, 10 Mbps (5 MHz) 10
Supply current IDDB, switching 10 Mbps IDDB 19.8 29.9 mA VDDA = VDDB = 5 V ± 10%; all channels 50% duty square wave 5 V, CL = 15 pF, 10 Mbps (5 MHz) 10
Supply current IDDA, switching 100 Mbps IDDA 10.6 16.3 mA VDDA = VDDB = 5 V ± 10%; all channels 50% duty square wave 5 V, CL = 15 pF, 100 Mbps (50 MHz) 10
Supply current IDDB, switching 100 Mbps IDDB 45.6 62.1 mA VDDA = VDDB = 5 V ± 10%; all channels 50% duty square wave 5 V, CL = 15 pF, 100 Mbps (50 MHz) 10
Junction-to-ambient thermal resistance RθJA 110 °C/W IC junction to ambient, SSOP16(B) 5

CAD (KiCad official)

  • Symbol: CA-IS3761HB
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ca-is3761hb-etched.step / ca-is3761hb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3761hb.step / ca-is3761hb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 0d88c3748184ff45, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF