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CA-IS3760HB

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Chipanalog Digital Isolators, SSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3760HB

Chipanalog · Digital Isolators · SSOP-16

CA-IS3760HB from Chipanalog, in a SSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage, recommended 2.375 V to 5.5 V with an absolute maximum of 7.0 V referenced to GNDA.
2 VI1 input Side A logic input for channel 1, with input threshold logic high minimum 2.0 V and logic low maximum 0.8 V (Schmitt trigger input).
3 VI2 input Side A logic input for channel 2, with input threshold logic high minimum 2.0 V and logic low maximum 0.8 V (Schmitt trigger input).
4 VI3 input Side A logic input for channel 3, with input threshold logic high minimum 2.0 V and logic low maximum 0.8 V (Schmitt trigger input).
5 VI4 input Side A logic input for channel 4 on the CA-IS3760, with input threshold logic high minimum 2.0 V and logic low maximum 0.8 V.
6 VI5 input Side A logic input for channel 5 on the CA-IS3760, with input threshold logic high minimum 2.0 V and logic low maximum 0.8 V.
7 VI6 input Side A logic input for channel 6 on the CA-IS3760, with input threshold logic high minimum 2.0 V and logic low maximum 0.8 V.
8 GNDA power_in Side A ground reference point for the Side A signals and VDDA supply.
9 GNDB power_in Side B ground reference point, isolated from GNDA by the isolation barrier.
10 VO6 output Side B logic output for channel 6 on the CA-IS3760, with approximately 50 Ω output impedance and rail-to-rail output; it takes the default fail-safe level (high for the H-suffix part) when the input is open or Side A power is lost.
11 VO5 output Side B logic output for channel 5 on the CA-IS3760, with approximately 50 Ω output impedance and rail-to-rail output; it takes the default fail-safe level (high for the H-suffix part) when the input is open or Side A power is lost.
12 VO4 output Side B logic output for channel 4 on the CA-IS3760, with approximately 50 Ω output impedance and rail-to-rail output; it takes the default fail-safe level (high for the H-suffix part) when the input is open or Side A power is lost.
13 VO3 output Side B logic output for channel 3, with approximately 50 Ω output impedance and rail-to-rail output; it takes the default fail-safe level (high for the H-suffix part) when the input is open or Side A power is lost.
14 VO2 output Side B logic output for channel 2, with approximately 50 Ω output impedance and rail-to-rail output; it takes the default fail-safe level (high for the H-suffix part) when the input is open or Side A power is lost.
15 VO1 output Side B logic output for channel 1, with approximately 50 Ω output impedance and rail-to-rail output; it takes the default fail-safe level (high for the H-suffix part) when the input is open or Side A power is lost.
16 VDDB power_in Side B supply voltage, recommended 2.375 V to 5.5 V with an absolute maximum of 7.0 V referenced to GNDB.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SSOP-16
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB 2.375 5.5 V 5
VDD undervoltage threshold, rising VDD（UVLO+） 1.95 2.24 2.375 V 5
VDD undervoltage threshold, falling VDD（UVLO‐） 1.88 2.1 2.325 V 5
VDD undervoltage hysteresis VHYS（UVLO） 70 140 250 mV 5
High-level output current IOH -4 mA VDDO1 = 5V 5
High-level output current IOH -2 mA VDDO = 3.3V 5
High-level output current IOH -1 mA VDDO = 2.5V 5
Low-level output current IOL 4 mA VDDO = 5V 5
Low-level output current IOL 2 mA VDDO = 3.3V 5
Low-level output current IOL 1 mA VDDO = 2.5V 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signal data rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Supply voltage VDDA, VDDB VDDA, VDDB -0.5 7 V 5
Input voltage Ax, Bx Vin -0.5 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature range TSTG -65 150 °C 5
Maximum power dissipation PD 494 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 输入 75MHz 50% 占空比方波 6
Maximum power dissipation, side A PDA 49 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 输入 75MHz 50% 占空比方波 6
Maximum power dissipation, side B PDB 445 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 输入 75MHz 50% 占空比方波 6
Output voltage logic low VOL 0.2 0.4 V IOL = 4mA; 图 8‐1 9
Input threshold logic high VIT+(IN) 2 V 9
Input threshold logic low VIT‐(IN) 0.8 V 9
Input high leakage current IIH 20 µA VIH = VDDA at Ax or Bx 9
Input low leakage current IIL -20 µA VIL = 0 V at Ax or Bx 9
Common-mode transient immunity CMTI 50 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; 图 8‐3 9
Supply current, DC signal (H variant, input high-to-low condition as printed) IDDA 7 10.7 mA VIN = VDDA (CA‐IS3760L); VIN = 0V(CA‐IS3760H) 10
Supply current, DC signal (H variant) IDDB 4.1 6.1 mA VIN = VDDA (CA‐IS3760L); VIN = 0V(CA‐IS3760H) 10
Supply current, AC 1Mbps (500kHz) IDDA 4.5 6.8 mA All channel inputs 50% duty, 5V square wave; CL = 15 pF 10
Supply current, AC 1Mbps (500kHz) IDDB 6.3 9.3 mA All channel inputs 50% duty, 5V square wave; CL = 15 pF 10
Supply current, AC 10Mbps (5MHz) IDDA 4.8 7.2 mA All channel inputs 50% duty, 5V square wave; CL = 15 pF 10
Supply current, AC 10Mbps (5MHz) IDDB 26.9 40.6 mA All channel inputs 50% duty, 5V square wave; CL = 15 pF 10
Supply current, AC 100Mbps (50MHz) IDDA 6.4 9.5 mA All channel inputs 50% duty, 5V square wave; CL = 15 pF 10
Supply current, AC 100Mbps (50MHz) IDDB 59 80 mA All channel inputs 50% duty, 5V square wave; CL = 15 pF 10
Data rate DR 0 150 Mbps 13
Minimum pulse width PWmin 5 ns 13
Propagation delay tPLH, tPHL 5 12 15 ns 图 8‐1 13
Pulse width distortion PWD 0.2 4.5 ns /tPLH ‐ tPHL/ 13
Channel-to-channel output skew, same direction tsk(o) 0.4 2.5 ns 同方向通道 13
Part-to-part channel output skew tsk(pp) 2 4.5 ns 13
Output rise time tr 2.5 4 ns 图 8‐1 13
Output fall time tf 2.5 4 ns 图 8‐1 13
Default output delay time from input power loss tDO 8 12 ns 图 8‐2 13
Startup time tSU 15 40 µs 13
Junction-to-ambient thermal resistance (SSOP16(B)) RθJA 110 °C/W 5

CAD (KiCad official)

  • Symbol: CA-IS3760HB
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ca-is3760hb-etched.step / ca-is3760hb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3760hb.step / ca-is3760hb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 0d88c3748184ff45, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF