component

CA-IS3742CLW

Public Made by Adom

by adom

Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsignal isolation devicesca-is3742clwfactory-2.0.0extractor-text

Verified CA-IS3742CLW

by Ray · last 10 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

10 Nov 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CA-IS3742CLW · SOIC-16-300mil · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 22-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-16W_7.5x10.3mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-7foqj970/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 33 kB, viewers/symbol.html 14 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ca-is3742clw.kicad_sym✓ ca-is3742clw.kicad_mod✓ ca-is3742clw.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers ca-is3742clw: viewers rendered from the public page · Ray
ca-is3742clw-etched.glb Publish 0.1.0 · Ray
ca-is3742clw-etched.step ca-is3742clw: factory component page (tier=lcsc) · Ray
ca-is3742clw-hero.glb ca-is3742clw: hero GLB from the etched model (keeps the MPN mark) · Ray
ca-is3742clw-hero.overlay.json Publish 0.1.0 · Ray
ca-is3742clw.glb Publish 0.1.0 · Ray
ca-is3742clw.kicad_mod Publish 0.1.0 · Ray
ca-is3742clw.kicad_sym Publish 0.1.0 · Ray
ca-is3742clw.lbr Publish 0.1.0 · Ray
ca-is3742clw.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 16 pins · Ray

CA-IS3742CLW

Chipanalog · Digital Isolators · SOIC-16-300mil

CA-IS3742CLW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage, 3.0 V to 5.5 V recommended operating range, with 0.1 µF and 1 µF bypass capacitors placed within 2 mm.
2 GNDA power_in Side A ground reference.
3 VI1 input Side A logic input for channel 1 (forward channel to VO1 on side B), CMOS threshold levels of 0.7×VDDI high and 0.3×VDDI low.
4 VI2 input Side A logic input for channel 2 (forward channel to VO2 on side B), CMOS threshold levels of 0.7×VDDI high and 0.3×VDDI low.
5 VO3 output Side A logic output for channel 3 (reverse channel from VI3 on side B), high-impedance when ENA is low.
6 VO4 output Side A logic output for channel 4 (reverse channel from VI4 on side B), high-impedance when ENA is low.
7 ENA input Side A output enable, active high or floating (internally pulled up to local VDD); low puts the VO3 and VO4 outputs in high impedance.
8 GNDA power_in Side A ground reference.
9 GNDB power_in Side B ground reference.
10 ENB input Side B output enable, active high or floating (internally pulled up to local VDD); low puts the VO1 and VO2 outputs in high impedance.
11 VI4 input Side B logic input for channel 4 (reverse channel to VO4 on side A), CMOS threshold levels of 0.7×VDDI high and 0.3×VDDI low.
12 VI3 input Side B logic input for channel 3 (reverse channel to VO3 on side A), CMOS threshold levels of 0.7×VDDI high and 0.3×VDDI low.
13 VO2 output Side B logic output for channel 2 (forward channel from VI2), high-impedance when ENB is low.
14 VO1 output Side B logic output for channel 1 (forward channel from VI1), high-impedance when ENB is low.
15 GNDB power_in Side B ground reference.
16 VDDB power_in Side B supply voltage, 3.0 V to 5.5 V recommended operating range, with 0.1 µF and 1 µF bypass capacitors placed within 2 mm.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB -0.5 7 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature TSTG -65 150 °C 5
ESD HBM VESD -8000 8000 V ANSI/ESDA/JEDEC JS-001, same-side pins 5
ESD CDM VESD -2000 2000 V JESD22-C101, all pins 5
Supply voltage VDDA, VDDB 3 3.3 5.5 V 5
UVLO rising threshold VDD(UVLO+) 2.55 2.7 2.85 V VDD rising 5
UVLO falling threshold VDD(UVLO-) 2.35 2.5 2.65 V VDD falling 5
UVLO hysteresis VHYS(UVLO) 150 200 250 mV 5
High-level output current IOH -4 mA VDDO = 5V 5
High-level output current IOH -2 mA VDDO = 3.3V 5
Low-level output current IOL 4 mA VDDO = 5V 5
Low-level output current IOL 2 mA VDDO = 3.3V 5
Ambient temperature TA -40 27 125 °C 5
Junction-to-ambient thermal resistance RθJA 83.4 °C/W SOIC16-WB(W) 6
Maximum power dissipation PD 120 mW CA-IS3742C; VDDA = VDDB = 5.5V, CL = 15pF, TJ = 150°C, 20MHz 50% duty square wave input 6
Maximum power dissipation side A PDA 56 mW CA-IS3742C 6
Maximum power dissipation side B PDB 64 mW CA-IS3742C 6
Output voltage low VOL 0.2 0.4 V IOL = 4mA; VDD 5V±10% 9
Input high leakage current IIH 20 µA VIH = VDDA at VIx or ENx 9
Input low leakage current IIL -20 µA VIL = 0V at VIx or ENx 9
Output impedance ZO 50 Ω 9
Common-mode transient immunity CMTI 150 kV/µs VI = VDDI or 0V, VCM = 1200V 9
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1MHz, VDD = 5V 9
Supply current A, enable off, input low (L) IDDA 3 4.8 mA CA-IS3742C; ENA = ENB = 0V; VIN = 0V (CL); VDD 5V±10% 10
Supply current B, enable off, input low (L) IDDB 3 4.8 mA CA-IS3742C; ENA = ENB = 0V; VIN = 0V (CL); VDD 5V±10% 10
Supply current A, enable off, input high (L) IDDA 5.8 9 mA CA-IS3742C; ENA = ENB = 0V; VIN = VDDI (CL); VDD 5V±10% 10
Supply current B, enable off, input high (L) IDDB 5.8 9 mA CA-IS3742C; ENA = ENB = 0V; VIN = VDDI (CL); VDD 5V±10% 10
Supply current A, 1Mbps IDDA 4.3 6.7 mA CA-IS3742C; 1Mbps (500kHz), CL = 15pF; 5V 10
Supply current B, 1Mbps IDDB 4.7 7.3 mA CA-IS3742C; 1Mbps (500kHz), CL = 15pF; 5V 10
Supply current A, 10Mbps IDDA 5.6 8.7 mA CA-IS3742C; 10Mbps (5MHz), CL = 15pF; 5V 10
Supply current B, 10Mbps IDDB 6 9.3 mA CA-IS3742C; 10Mbps (5MHz), CL = 15pF; 5V 10
Supply current A, 40Mbps IDDA 8.7 13.4 mA CA-IS3742C; 40Mbps (20MHz), CL = 15pF; 5V 10
Supply current B, 40Mbps IDDB 9.4 14.4 mA CA-IS3742C; 40Mbps (20MHz), CL = 15pF; 5V 10
Supply current A, enable off, input low (L) IDDA 2.9 4.7 mA CA-IS3742C; ENA = ENB = 0V; VIN = 0V (CL); VDD 3.3V±10% 11
Supply current B, enable off, input low (L) IDDB 2.9 4.7 mA CA-IS3742C; ENA = ENB = 0V; VIN = 0V (CL); VDD 3.3V±10% 11
Supply current A, enable off, input high (L) IDDA 5.8 8.9 mA CA-IS3742C; ENA = ENB = 0V; VIN = VDDI (CL); VDD 3.3V±10% 11
Supply current B, enable off, input high (L) IDDB 5.8 8.9 mA CA-IS3742C; ENA = ENB = 0V; VIN = VDDI (CL); VDD 3.3V±10% 11
Supply current A, 1Mbps IDDA 4.2 6.6 mA CA-IS3742C; 1Mbps (500kHz), CL = 15pF; 3.3V 11
Supply current B, 1Mbps IDDB 4.3 6.8 mA CA-IS3742C; 1Mbps (500kHz), CL = 15pF; 3.3V 11
Supply current A, 10Mbps IDDA 5.1 8 mA CA-IS3742C; 10Mbps (5MHz), CL = 15pF; 3.3V 11
Supply current B, 10Mbps IDDB 5.2 8.1 mA CA-IS3742C; 10Mbps (5MHz), CL = 15pF; 3.3V 11
Supply current A, 40Mbps IDDA 6 9.4 mA CA-IS3742C; 40Mbps (20MHz), CL = 15pF; 3.3V 11
Supply current B, 40Mbps IDDB 6.4 10 mA CA-IS3742C; 40Mbps (20MHz), CL = 15pF; 3.3V 11
Propagation delay tPLH, tPHL 22 35 ns Figure 8-1 12
Pulse width distortion PWD 2.5 10 ns /tPLH - tPHL/ 12
Channel-to-channel output skew tsk(o) 1 3 ns same-direction channels 12
Part-to-part skew tsk(pp) 1 7 ns 12
Output rise time tr 2.5 4.8 ns Figure 8-1 12
Output fall time tf 2.5 4.8 ns Figure 8-1 12
Disable delay, high to high-Z tPHZ 8 12 ns Figure 8-3 12
Disable delay, low to high-Z tPLZ 8 12 ns Figure 8-3 12
Enable delay, high-Z to high tPZH 10 15 ns CA-IS374xCL 12
Enable delay, high-Z to high tPZH 15 22 ns CA-IS374xCH 12
Enable delay, high-Z to low tPZL 10 15 ns CA-IS374xCL 12
Enable delay, high-Z to low tPZL 15 22 ns CA-IS374xCH 12
Delay from power-down to default output tDO 10 15 ns Figure 8-4 12
Start-up time tSU 25 37 µs 12

CAD (KiCad official)

  • Symbol: CA-IS3742CLW
  • Footprint: Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3742clw-etched.step / ca-is3742clw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3742clw.step / ca-is3742clw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (22 pp, sha256 b56bd5219f5a1f9e, retrieved 2026-11-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF