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CA-IS3741LB

Public Made by Adom

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Chipanalog Digital Isolators, SSOP-16-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3741LB

Chipanalog · Digital Isolators · SSOP-16-150mil

CA-IS3741LB from Chipanalog, in a SSOP-16-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage, 2.375 V to 5.5 V recommended, with a 0.1 µF to 1 µF bypass capacitor.
2 GNDA power_in Side A ground reference.
3 VI1 input Side A logic input for channel 1.
4 VI2 input Side A logic input for channel 2.
5 VI3 input Side A logic input for channel 3 (CA-IS3741 forward channel).
6 VO4 output Side A logic output for channel 4 (CA-IS3741 reverse channel), tri-stated when ENA is low.
7 ENA input Side A output enable, active high or floating, internally pulled up to VDDA; low puts VO4 in high impedance.
8 GNDA power_in Side A ground reference.
9 GNDB power_in Side B ground reference.
10 ENB input Side B output enable, active high or floating, internally pulled up to VDDB; low puts VO1 to VO3 in high impedance.
11 VI4 input Side B logic input for channel 4 (CA-IS3741 reverse channel).
12 VO3 output Side B logic output for channel 3, tri-stated when ENB is low.
13 VO2 output Side B logic output for channel 2, tri-stated when ENB is low.
14 VO1 output Side B logic output for channel 1, tri-stated when ENB is low.
15 GNDB power_in Side B ground reference.
16 VDDB power_in Side B supply voltage, 2.375 V to 5.5 V recommended, with a 0.1 µF to 1 µF bypass capacitor.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SSOP-16-150mil
Category Communication Interface Chip/UART/485/232
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB VDDA, VDDB -0.5 7 V 5
Input voltage Ax, Bx, ENx Vin -0.5 V max VDD+0.5, not to exceed 7 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature TSTG -65 150 °C 5
ESD HBM VESD -6000 6000 V ANSI/ESDA/JEDEC JS-001, all pins 5
ESD CDM VESD -2000 2000 V JESD22-C101, all pins 5
Supply voltage VDDA, VDDB 2.375 5.5 V typ 3.3/5.0 5
UVLO rising threshold VDD(UVLO+) 1.95 2.24 2.37 V 5
UVLO falling threshold VDD(UVLO-) 1.88 2.1 2.325 V 5
UVLO hysteresis VHYS(UVLO) 70 140 250 mV 5
High-level output current IOH -4 mA VDDO = 5V (-2 at 3.3V, -1 at 2.5V) 5
Low-level output current IOL 4 mA VDDO = 5V (2 at 3.3V, 1 at 2.5V) 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signaling rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Junction-to-ambient thermal resistance RθJA 110 °C/W SSOP16-NB(B) 6
Maximum power dissipation PD 334 mW CA-IS3741; VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave 6
Side A max power dissipation PDA 100 mW CA-IS3741 6
Side B max power dissipation PDB 234 mW CA-IS3741 6
Output voltage high VOH -0.4 4.8 V VDDA = VDDB = 5V±10%; IOH = -4mA; min is VDDO-0.4 9
Output voltage low VOL 0.2 0.4 V VDDA = VDDB = 5V±10%; IOL = 4mA 9
Input threshold logic high VIT+(IN) 2 V VDDA = VDDB = 5V±10% 9
Input threshold logic low VIT-(IN) 0.8 V VDDA = VDDB = 5V±10% 9
Input high leakage current IIH 20 µA VIH = VDDA at Ax or Bx or ENx 9
Input low leakage current IIL -20 µA VIL = 0 V at Ax or Bx or ENx 9
Output impedance ZO 50 Ω 9
Common-mode transient immunity CMTI 100 150 kV/µs VI = VDDI or 0 V, VCM = 1200 V 9
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V 9
Output voltage high VOH -0.4 3.1 V VDDA = VDDB = 3.3V±10%; IOH = -2mA; min is VDDO-0.4 9
Output voltage high VOH -0.4 2.3 V VDDA = VDDB = 2.5V±5%; IOH = -1mA; min is VDDO-0.4 9
IDDA enable off, VIN low (L) IDDA 1.5 2.4 mA CA-IS3741; 5V; ENA = ENB = 0 V; VIN = 0V 10
IDDB enable off, VIN low (L) IDDB 2.3 3.6 mA CA-IS3741; 5V; ENA = ENB = 0 V; VIN = 0V 10
IDDA DC signal, VIN = VDDI (L) IDDA 4.2 6.9 mA CA-IS3741; 5V; ENA = ENB = VDDI; VIN = VDDI 10
IDDB DC signal, VIN = VDDI (L) IDDB 3.5 5.4 mA CA-IS3741; 5V; ENA = ENB = VDDI; VIN = VDDI 10
IDDA 1Mbps IDDA 3.3 5.2 mA CA-IS3741; 5V; 1Mbps (500kHz), CL = 15 pF 10
IDDB 1Mbps IDDB 4.1 6.2 mA CA-IS3741; 5V; 1Mbps (500kHz), CL = 15 pF 10
IDDA 10Mbps IDDA 6.9 9.9 mA CA-IS3741; 5V; 10Mbps (5MHz), CL = 15 pF 10
IDDB 10Mbps IDDB 14 19.5 mA CA-IS3741; 5V; 10Mbps (5MHz), CL = 15 pF 10
IDDA 100Mbps IDDA 14.3 19.8 mA CA-IS3741; 5V; 100Mbps (50MHz), CL = 15 pF 10
IDDB 100Mbps IDDB 32.5 44 mA CA-IS3741; 5V; 100Mbps (50MHz), CL = 15 pF 10
Data rate DR 150 Mbps 5V±10% 13
Minimum pulse width PWmin 5 ns 5V±10% 13
Propagation delay tPLH, tPHL 5 12 16 ns Figure 8-1; 5V±10% 13
Pulse width distortion PWD 0.2 4.5 ns /tPLH - tPHL/; 5V±10% 13
Channel-to-channel output skew tsk(o) 0.4 2.5 ns same-direction channels; 5V±10% 13
Part-to-part skew tsk(pp) 2 4.5 ns 5V±10% 13
Output rise time tr 2.5 4 ns Figure 8-1; 5V±10% 13
Output fall time tf 2.5 4 ns Figure 8-1; 5V±10% 13
Disable delay, high to Hi-Z tPHZ 8 13 ns Figure 8-2; 5V±10% 13
Disable delay, low to Hi-Z tPLZ 8 17 ns Figure 8-2; 5V±10% 13
Enable delay, Hi-Z to high tPZH 10 20 ns CA-IS374xL; Figure 8-2; 5V±10% 13
Enable delay, Hi-Z to low tPZL 10 25 ns CA-IS374xL; Figure 8-2; 5V±10% 13
Default output delay tDO 8 12 µs Figure 8-3; 5V±10% 13
Start-up time tSU 15 40 µs 5V±10% 13
Isolation rating VISO 3750 VRMS SSOP16-NB; UL 1577, t = 60 s 7

CAD (KiCad official)

  • Symbol: CA-IS3741LB
  • Footprint: Package_SO:SSOP-16_5.3x6.2mm_P0.65mm
  • 3D model: SSOP-16-150mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3741lb-etched.step / ca-is3741lb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3741lb.step / ca-is3741lb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (25 pp, sha256 fd7bb5373a55db4c, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF