component

CA-IS3741HW

Public Made by Adom

by adom

Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsca-is3741hwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CA-IS3741HW

Chipanalog · Digital Isolators · SOIC-16-300mil

CA-IS3741HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage, 2.375 V to 5.5 V recommended, with a 0.1 µF to 1 µF bypass capacitor.
2 GNDA power_in Side A ground reference.
3 VI1 input Side A logic input for channel 1.
4 VI2 input Side A logic input for channel 2.
5 VI3 input Side A logic input for channel 3 (CA-IS3741 has three forward channels).
6 VO4 tri_state Side A logic output for the reverse channel 4, placed in high impedance when ENA is low.
7 ENA input Side A output enable, active high or floating (internally pulled up to local VDD); low puts VO4 in high impedance.
8 GNDA power_in Side A ground reference.
9 GNDB power_in Side B ground reference.
10 ENB input Side B output enable, active high or floating (internally pulled up to local VDD); low puts VO1 to VO3 in high impedance.
11 VI4 input Side B logic input for reverse channel 4.
12 VO3 tri_state Side B logic output for channel 3, placed in high impedance when ENB is low.
13 VO2 tri_state Side B logic output for channel 2, placed in high impedance when ENB is low.
14 VO1 tri_state Side B logic output for channel 1, placed in high impedance when ENB is low.
15 GNDB power_in Side B ground reference.
16 VDDB power_in Side B supply voltage, 2.375 V to 5.5 V recommended, with a 0.1 µF to 1 µF bypass capacitor.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB -0.5 7 V 5
Input voltage Ax, Bx, ENx Vin -0.5 V max VDD+0.5, not to exceed 7 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature TSTG -65 150 °C 5
ESD HBM VESD -6000 6000 V ANSI/ESDA/JEDEC JS-001, all pins 5
ESD CDM VESD -2000 2000 V JESD22-C101, all pins 5
Supply voltage VDDA, VDDB 2.375 5.5 V typ 3.3/5.0 5
UVLO rising threshold VDD(UVLO+) 1.95 2.24 2.37 V VDD rising 5
UVLO falling threshold VDD(UVLO-) 1.88 2.1 2.325 V VDD falling 5
UVLO hysteresis VHYS(UVLO) 70 140 250 mV 5
High-level output current IOH -4 mA VDDO = 5V (-2 at 3.3V, -1 at 2.5V) 5
Low-level output current IOL 4 mA VDDO = 5V (2 at 3.3V, 1 at 2.5V) 5
High-level input threshold VIH 2 V 5
Low-level input threshold VIL 0.8 V 5
Signal rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Junction-to-ambient thermal resistance RθJA 83.4 °C/W SOIC16-WB(W) 6
Maximum power dissipation PD 334 mW CA-IS3741, VDDA=VDDB=5.5V, CL=15pF, TJ=150°C, 75MHz 50% square wave 6
High-level output voltage VOH 4.8 V IOH=-4mA; min is VDDO-0.4 V; 5V±10% 9
Low-level output voltage VOL 0.2 0.4 V IOL=4mA; 5V±10% 9
Input threshold logic high VIT+(IN) 2 V 9
Input threshold logic low VIT-(IN) 0.8 V 9
Input high leakage current IIH 20 µA VIH = VDDA at Ax or Bx or ENx 9
Input low leakage current IIL -20 µA VIL = 0 V at Ax or Bx or ENx 9
Output impedance ZO 50 Ω 9
Common-mode transient immunity CMTI 100 150 kV/µs VI = VDDI or 0 V, VCM = 1200 V 9
High-level output voltage VOH 3.1 V IOH=-2mA; min is VDDO-0.4 V; 3.3V±10% 9
High-level output voltage VOH 2.3 V IOH=-1mA; min is VDDO-0.4 V; 2.5V±5% 9
Supply current IDDA, enable off, input high IDDA 1.5 2.4 mA ENA=ENB=0V; VIN=VDDI (CA-IS3741H); 5V 10
Supply current IDDB, enable off, input high IDDB 2.3 3.6 mA ENA=ENB=0V; VIN=VDDI (CA-IS3741H); 5V 10
Supply current IDDA, enable off, input 0V IDDA 4.1 6.8 mA ENA=ENB=0V; VIN=0V (CA-IS3741H); 5V 10
Supply current IDDB, enable off, input 0V IDDB 3.2 5.1 mA ENA=ENB=0V; VIN=0V (CA-IS3741H); 5V 10
Supply current IDDA, DC, input high IDDA 1.6 2.5 mA ENA=ENB=VDDI; VIN=VDDI (CA-IS3741H); 5V 10
Supply current IDDB, DC, input high IDDB 2.5 3.9 mA ENA=ENB=VDDI; VIN=VDDI (CA-IS3741H); 5V 10
Supply current IDDA, DC, input 0V IDDA 4.2 6.9 mA ENA=ENB=VDDI; VIN=0V (CA-IS3741H); 5V 10
Supply current IDDB, DC, input 0V IDDB 3.5 5.4 mA ENA=ENB=VDDI; VIN=0V (CA-IS3741H); 5V 10
Supply current IDDA, AC 1Mbps IDDA 3.3 5.2 mA 1Mbps (500kHz), 5V square wave, CL=15pF per channel 10
Supply current IDDB, AC 1Mbps IDDB 4.1 6.2 mA 1Mbps (500kHz), 5V square wave, CL=15pF per channel 10
Supply current IDDA, AC 100Mbps IDDA 14.3 19.8 mA 100Mbps (50MHz), 5V square wave, CL=15pF per channel 10
Supply current IDDB, AC 100Mbps IDDB 32.5 44 mA 100Mbps (50MHz), 5V square wave, CL=15pF per channel 10
Data rate DR 150 Mbps 5V±10% 13
Minimum pulse width PWmin 5 ns 5V±10% 13
Propagation delay tPLH, tPHL 5 12 16 ns Figure 8-1; 5V±10% 13
Pulse width distortion PWD 0.2 4.5 ns /tPLH - tPHL/ 13
Channel-to-channel output skew tsk(o) 0.4 2.5 ns same-direction channels 13
Part-to-part skew tsk(pp) 2 4.5 ns 13
Output rise time tr 2.5 4 ns Figure 8-1 13
Output fall time tf 2.5 4 ns Figure 8-1 13
Disable delay, high to high-Z tPHZ 8 13 ns Figure 8-2 13
Disable delay, low to high-Z tPLZ 8 17 ns Figure 8-2 13
Enable delay, high-Z to high tPZH 15 30 ns CA-IS374xH; Figure 8-2 13
Enable delay, high-Z to low tPZL 15 30 ns CA-IS374xH; Figure 8-2 13
Default output delay from UVLO tDO 8 12 µs Figure 8-3 13
Start-up time tSU 15 40 µs 13

CAD (KiCad official)

  • Symbol: CA-IS3741HW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3741hw-etched.step / ca-is3741hw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3741hw.step / ca-is3741hw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (25 pp, sha256 fd7bb5373a55db4c, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF