component
CA-IS3740VLN
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CA-IS3740VLN
Chipanalog · Digital Isolators · SOIC-16
CA-IS3740VLN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A supply voltage, recommended range 1.7 V to 5.5 V, with a 0.1 µF to 1 µF bypass capacitor to GNDA. |
| 2 | GNDA | power_in | Side A ground reference. |
| 3 | VI1 | input | Side A logic input for channel 1, passed to VO1 and defaulting low if the input is open or VDDA is unpowered. |
| 4 | VI2 | input | Side A logic input for channel 2, passed to VO2 and defaulting low if the input is open or VDDA is unpowered. |
| 5 | VI3 | input | Side A logic input for channel 3, passed to VO3 and defaulting low if the input is open or VDDA is unpowered. |
| 6 | VI4 | input | Side A logic input for channel 4, passed to VO4 and defaulting low if the input is open or VDDA is unpowered. |
| 7 | NC | unconnected | No internal connection; it may be left floating or tied to VDD or GND. |
| 8 | GNDA | power_in | Side A ground reference. |
| 9 | GNDB | power_in | Side B ground reference. |
| 10 | ENB | input | Side B output enable, internally pulled up to VDDB; high or floating enables outputs VO1 to VO4, low puts them in high impedance. |
| 11 | VO4 | tri_state | Side B logic output for channel 4, high impedance when ENB is low. |
| 12 | VO3 | tri_state | Side B logic output for channel 3, high impedance when ENB is low. |
| 13 | VO2 | tri_state | Side B logic output for channel 2, high impedance when ENB is low. |
| 14 | VO1 | tri_state | Side B logic output for channel 1, high impedance when ENB is low. |
| 15 | GNDB | power_in | Side B ground reference. |
| 16 | VDDB | power_in | Side B supply voltage, recommended range 1.7 V to 5.5 V, with a 0.1 µF to 1 µF bypass capacitor to GNDB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16 |
| Category | Isolators |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB | VDDA, VDDB | -0.5 | 7 | V | 5 | ||
| Input voltage AIx, BOx, ENB | Vin | -0.5 | V | 5 | |||
| Output current | IO | -20 | 20 | mA | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| ESD Human Body Model, all pins | VESD | -6000 | 6000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| ESD Charged Device Model, all pins | VESD | -2000 | 2000 | V | JEDEC JESD22-C101, all pins | 5 | |
| Supply voltage VDDA, VDDB (recommended) | VDDA, VDDB | 1.7 | 5.5 | V | 5 | ||
| UVLO threshold, rising supply | VDD(UVLO+) | 1.5 | 1.57 | 1.64 | V | VDD rising | 5 |
| UVLO threshold, falling supply | VDD(UVLO-) | 1.4 | 1.49 | 1.5 | V | VDD falling | 5 |
| UVLO hysteresis | VHYS(UVLO) | 50 | 80 | 100 | mV | 5 | |
| High-level output current | IOH | -4 | mA | VDDO = 5 V | 5 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5 V | 5 | ||
| Input threshold logic high | VIH | 1.5 | V | 5 | |||
| Input threshold logic low | VIL | 0.8 | V | 5 | |||
| Signaling data rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Maximum power dissipation | PD | 334 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75 MHz 50% duty square-wave input | 6 | ||
| External clearance | CLR | 4 | mm | Input to output, shortest air path | 7 | ||
| External creepage | CPG | 4 | mm | Input to output, shortest path along package body | 7 | ||
| Internal gap (DTI) | DTI | 28 | μm | Minimum internal gap | 7 | ||
| Comparative tracking index | CTI | 600 | V | DIN EN 60112 (VDE 0303-11); IEC 60112 | 7 | ||
| Maximum repetitive peak isolation voltage | VIORM | 566 | VPK | AC voltage (bipolar) | 7 | ||
| Maximum working isolation voltage | VIOWM | 400 | VRMS | AC voltage; time-dependent dielectric breakdown (TDDB) test | 7 | ||
| Maximum working isolation voltage | VIOWM | 566 | VDC | DC voltage | 7 | ||
| Maximum transient isolation voltage | VIOTM | 5300 | VPK | VTEST = VIOTM, t = 60 s (certification); VTEST = 1.2 × VIOTM, t = 1 s (100% production test) | 7 | ||
| Maximum surge isolation voltage | VIOSM | 4070 | VPK | IEC 60065, 1.2/50 μs waveform, VTEST = 1.3 × VIOSM (certification) | 7 | ||
| Apparent charge, method a (after subclass 2/3) | qpd | 5 | pC | Method a, I/O safety test subclass 2/3; Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s | 7 | ||
| Apparent charge, method a (after subclass 1) | qpd | 5 | pC | Method a, environmental test subclass 1; Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s | 7 | ||
| Apparent charge, method b1 (routine test) | qpd | 5 | pC | Method b1, routine test; Vini = 1.2 × VIOTM, tini = 1 s; Vpd(m) = 1.5 × VIORM, tm = 1 s | 7 | ||
| Maximum isolation voltage | VISO | 3750 | VRMS | VTEST = VISO, t = 60 s (certification); VTEST = 1.2 × VISO, t = 1 s (100% production test) | 7 | ||
| Positive input threshold | VIT+(IN) | 2 | V | 9 | |||
| Negative input threshold | VIT-(IN) | 0.8 | V | 9 | |||
| Input high leakage current | IIH | 20 | µA | VIH = VDDA at AIx or BOx or ENB | 9 | ||
| Input low leakage current | IIL | -20 | µA | VIL = 0 V at AIx or BOx or ENB | 9 | ||
| Common-mode transient immunity | CMTI | 100 | 150 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; Fig 8-4 | 9 | |
| Output voltage logic low | VOL | 0.2 | 0.4 | V | IOL = 4 mA; Fig 8-2 | 9 | |
| Supply current, enable off, ENB = 0 V, VIN = 0 V, side A | IDDA | 1.3 | 2.1 | mA | ENB = 0 V; VIN = 0V | 9 | |
| Supply current, enable off, ENB = 0 V, VIN = 0 V, side B | IDDB | 2.5 | 3.5 | mA | ENB = 0 V; VIN = 0V | 10 | |
| Supply current, DC signal, ENB = VDDB, VIN = 0 V, side A | IDDA | 1.3 | 2.1 | mA | ENB = VDDB; VIN = 0V | 10 | |
| Supply current, DC signal, ENB = VDDB, VIN = 0 V, side B | IDDB | 2.7 | 3.9 | mA | ENB = VDDB; VIN = 0V | 10 | |
| Supply current, AC signal 100 Mbps, side A | IDDA | 4.7 | 6.8 | mA | ENB = VDDB; all inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 100 Mbps (50 MHz) | 10 | |
| Supply current, AC signal 100 Mbps, side B | IDDB | 41 | 54.7 | mA | ENB = VDDB; all inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 100 Mbps (50 MHz) | 10 | |
| Minimum pulse width | PWmin | 5 | ns | 13 | |||
| Propagation delay | tPLH, tPHL | 5 | 12 | 16 | ns | Fig 8-1 | 13 |
| Pulse width distortion | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 13 | |
| Chip-to-chip output skew | tsk(pp) | 2 | 4.5 | ns | 13 | ||
| Output rise time | tr | 2.5 | 4 | ns | Fig 8-1 | 13 | |
| Output fall time | tf | 2.5 | 4 | ns | Fig 8-1 | 13 | |
| Disable propagation delay, high to high-Z | tPHZ | 8 | 13 | ns | Fig 8-2 | 13 | |
| Disable propagation delay, low to high-Z | tPLZ | 8 | 17 | ns | 13 | ||
| Enable propagation delay, high-Z to high | tPZH | 10 | 20 | ns | 13 | ||
| Enable propagation delay, high-Z to low | tPZL | 10 | 25 | ns | 13 | ||
| Default output delay from input-side UVLO | tDO | 0.1 | 0.3 | µs | Fig 8-3 | 13 | |
| Startup time | tSU | 15 | 40 | µs | 13 | ||
| Junction-to-ambient thermal resistance | RθJA | 96.2 | °C/W | 6 | |||
| High-level output voltage | VOH | 4.8 | V | IOH = -4 mA; Fig 8-2 (printed minimum is VDDO1 - 0.4) | 9 |
CAD (KiCad official)
- Symbol:
CA-IS3740VLN - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ca-is3740vln-etched.step/ca-is3740vln-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3740vln.step/ca-is3740vln.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (24 pp, sha256
d01faaa7371ab098, retrieved 2026-11-04, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CA-IS3740VLN
**Chipanalog** · Digital Isolators · SOIC-16
CA-IS3740VLN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A supply voltage, recommended range 1.7 V to 5.5 V, with a 0.1 µF to 1 µF bypass capacitor to GNDA. |
| 2 | GNDA | power_in | Side A ground reference. |
| 3 | VI1 | input | Side A logic input for channel 1, passed to VO1 and defaulting low if the input is open or VDDA is unpowered. |
| 4 | VI2 | input | Side A logic input for channel 2, passed to VO2 and defaulting low if the input is open or VDDA is unpowered. |
| 5 | VI3 | input | Side A logic input for channel 3, passed to VO3 and defaulting low if the input is open or VDDA is unpowered. |
| 6 | VI4 | input | Side A logic input for channel 4, passed to VO4 and defaulting low if the input is open or VDDA is unpowered. |
| 7 | NC | unconnected | No internal connection; it may be left floating or tied to VDD or GND. |
| 8 | GNDA | power_in | Side A ground reference. |
| 9 | GNDB | power_in | Side B ground reference. |
| 10 | ENB | input | Side B output enable, internally pulled up to VDDB; high or floating enables outputs VO1 to VO4, low puts them in high impedance. |
| 11 | VO4 | tri_state | Side B logic output for channel 4, high impedance when ENB is low. |
| 12 | VO3 | tri_state | Side B logic output for channel 3, high impedance when ENB is low. |
| 13 | VO2 | tri_state | Side B logic output for channel 2, high impedance when ENB is low. |
| 14 | VO1 | tri_state | Side B logic output for channel 1, high impedance when ENB is low. |
| 15 | GNDB | power_in | Side B ground reference. |
| 16 | VDDB | power_in | Side B supply voltage, recommended range 1.7 V to 5.5 V, with a 0.1 µF to 1 µF bypass capacitor to GNDB. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16 |
| Category | Isolators |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB | VDDA, VDDB | -0.5 | | 7 | V | | 5 |
| Input voltage AIx, BOx, ENB | Vin | -0.5 | | | V | | 5 |
| Output current | IO | -20 | | 20 | mA | | 5 |
| Junction temperature | TJ | | | 150 | °C | | 5 |
| Storage temperature range | TSTG | -65 | | 150 | °C | | 5 |
| ESD Human Body Model, all pins | VESD | -6000 | | 6000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 5 |
| ESD Charged Device Model, all pins | VESD | -2000 | | 2000 | V | JEDEC JESD22-C101, all pins | 5 |
| Supply voltage VDDA, VDDB (recommended) | VDDA, VDDB | 1.7 | | 5.5 | V | | 5 |
| UVLO threshold, rising supply | VDD(UVLO+) | 1.5 | 1.57 | 1.64 | V | VDD rising | 5 |
| UVLO threshold, falling supply | VDD(UVLO-) | 1.4 | 1.49 | 1.5 | V | VDD falling | 5 |
| UVLO hysteresis | VHYS(UVLO) | 50 | 80 | 100 | mV | | 5 |
| High-level output current | IOH | -4 | | | mA | VDDO = 5 V | 5 |
| Low-level output current | IOL | | | 4 | mA | VDDO = 5 V | 5 |
| Input threshold logic high | VIH | 1.5 | | | V | | 5 |
| Input threshold logic low | VIL | | | 0.8 | V | | 5 |
| Signaling data rate | DR | 0 | | 150 | Mbps | | 5 |
| Ambient temperature | TA | -40 | 27 | 125 | °C | | 5 |
| Maximum power dissipation | PD | | | 334 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75 MHz 50% duty square-wave input | 6 |
| External clearance | CLR | 4 | | | mm | Input to output, shortest air path | 7 |
| External creepage | CPG | 4 | | | mm | Input to output, shortest path along package body | 7 |
| Internal gap (DTI) | DTI | 28 | | | μm | Minimum internal gap | 7 |
| Comparative tracking index | CTI | 600 | | | V | DIN EN 60112 (VDE 0303-11); IEC 60112 | 7 |
| Maximum repetitive peak isolation voltage | VIORM | | | 566 | VPK | AC voltage (bipolar) | 7 |
| Maximum working isolation voltage | VIOWM | | | 400 | VRMS | AC voltage; time-dependent dielectric breakdown (TDDB) test | 7 |
| Maximum working isolation voltage | VIOWM | | | 566 | VDC | DC voltage | 7 |
| Maximum transient isolation voltage | VIOTM | | | 5300 | VPK | VTEST = VIOTM, t = 60 s (certification); VTEST = 1.2 × VIOTM, t = 1 s (100% production test) | 7 |
| Maximum surge isolation voltage | VIOSM | | | 4070 | VPK | IEC 60065, 1.2/50 μs waveform, VTEST = 1.3 × VIOSM (certification) | 7 |
| Apparent charge, method a (after subclass 2/3) | qpd | | | 5 | pC | Method a, I/O safety test subclass 2/3; Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM, tm = 10 s | 7 |
| Apparent charge, method a (after subclass 1) | qpd | | | 5 | pC | Method a, environmental test subclass 1; Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM, tm = 10 s | 7 |
| Apparent charge, method b1 (routine test) | qpd | | | 5 | pC | Method b1, routine test; Vini = 1.2 × VIOTM, tini = 1 s; Vpd(m) = 1.5 × VIORM, tm = 1 s | 7 |
| Maximum isolation voltage | VISO | | | 3750 | VRMS | VTEST = VISO, t = 60 s (certification); VTEST = 1.2 × VISO, t = 1 s (100% production test) | 7 |
| Positive input threshold | VIT+(IN) | | | 2 | V | | 9 |
| Negative input threshold | VIT-(IN) | | | 0.8 | V | | 9 |
| Input high leakage current | IIH | | | 20 | µA | VIH = VDDA at AIx or BOx or ENB | 9 |
| Input low leakage current | IIL | -20 | | | µA | VIL = 0 V at AIx or BOx or ENB | 9 |
| Common-mode transient immunity | CMTI | 100 | 150 | | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; Fig 8-4 | 9 |
| Output voltage logic low | VOL | | 0.2 | 0.4 | V | IOL = 4 mA; Fig 8-2 | 9 |
| Supply current, enable off, ENB = 0 V, VIN = 0 V, side A | IDDA | | 1.3 | 2.1 | mA | ENB = 0 V; VIN = 0V | 9 |
| Supply current, enable off, ENB = 0 V, VIN = 0 V, side B | IDDB | | 2.5 | 3.5 | mA | ENB = 0 V; VIN = 0V | 10 |
| Supply current, DC signal, ENB = VDDB, VIN = 0 V, side A | IDDA | | 1.3 | 2.1 | mA | ENB = VDDB; VIN = 0V | 10 |
| Supply current, DC signal, ENB = VDDB, VIN = 0 V, side B | IDDB | | 2.7 | 3.9 | mA | ENB = VDDB; VIN = 0V | 10 |
| Supply current, AC signal 100 Mbps, side A | IDDA | | 4.7 | 6.8 | mA | ENB = VDDB; all inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 100 Mbps (50 MHz) | 10 |
| Supply current, AC signal 100 Mbps, side B | IDDB | | 41 | 54.7 | mA | ENB = VDDB; all inputs 50% duty square wave, 5 V amplitude; CL = 15 pF; 100 Mbps (50 MHz) | 10 |
| Minimum pulse width | PWmin | 5 | | | ns | | 13 |
| Propagation delay | tPLH, tPHL | 5 | 12 | 16 | ns | Fig 8-1 | 13 |
| Pulse width distortion | PWD | 0.2 | | 4.5 | ns | /tPLH - tPHL/ | 13 |
| Chip-to-chip output skew | tsk(pp) | 2 | | 4.5 | ns | | 13 |
| Output rise time | tr | 2.5 | | 4 | ns | Fig 8-1 | 13 |
| Output fall time | tf | 2.5 | | 4 | ns | Fig 8-1 | 13 |
| Disable propagation delay, high to high-Z | tPHZ | 8 | | 13 | ns | Fig 8-2 | 13 |
| Disable propagation delay, low to high-Z | tPLZ | 8 | | 17 | ns | | 13 |
| Enable propagation delay, high-Z to high | tPZH | 10 | | 20 | ns | | 13 |
| Enable propagation delay, high-Z to low | tPZL | 10 | | 25 | ns | | 13 |
| Default output delay from input-side UVLO | tDO | 0.1 | | 0.3 | µs | Fig 8-3 | 13 |
| Startup time | tSU | 15 | | 40 | µs | | 13 |
| Junction-to-ambient thermal resistance | RθJA | | 96.2 | | °C/W | | 6 |
| High-level output voltage | VOH | | 4.8 | | V | IOH = -4 mA; Fig 8-2 (printed minimum is VDDO1 - 0.4) | 9 |
## CAD (KiCad official)
- Symbol: `CA-IS3740VLN`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `ca-is3740vln-etched.step` / `ca-is3740vln-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is3740vln.step` / `ca-is3740vln.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Chipanalog datasheet](docs/ca-is3740vln-datasheet.pdf) (24 pp, sha256 `d01faaa7371ab098`, retrieved 2026-11-04, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ca-is3740vln-datasheet.pdf)