component
CA-IS3740HW
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 18d ago |
| viewers | 18d ago |
| ca-is3740hw-etched.glb | 18d ago |
| ca-is3740hw-etched.step | 18d ago |
| ca-is3740hw-hero.glb | 18d ago |
| ca-is3740hw-hero.overlay.json | 18d ago |
| ca-is3740hw.glb | 18d ago |
| ca-is3740hw.kicad_mod | 18d ago |
| ca-is3740hw.kicad_sym | 18d ago |
| ca-is3740hw.lbr | 18d ago |
| ca-is3740hw.step | 18d ago |
| package.json | 18d ago |
| page.json | 18d ago |
| README.md | 18d ago |
CA-IS3740HW
Chipanalog · Digital Isolators · SOIC-16-300mil
CA-IS3740HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A supply voltage, recommended 2.375 V to 5.5 V with a 0.1 µF to 1 µF bypass capacitor. |
| 2 | GNDA | power_in | Side A ground reference. |
| 3 | VI1 | input | Side A logic input for channel 1 (CA-IS3740, transmitted to VO1). |
| 4 | VI2 | input | Side A logic input for channel 2 (transmitted to VO2). |
| 5 | VI3 | input | Side A logic input for channel 3 (CA-IS3740, transmitted to VO3). |
| 6 | VI4 | input | Side A logic input for channel 4 (CA-IS3740, transmitted to VO4). |
| 7 | NC | unconnected | No internal connection on CA-IS3740; may be left floating or connected to VDD or GND. |
| 8 | GNDA | power_in | Side A ground reference. |
| 9 | GNDB | power_in | Side B ground reference. |
| 10 | ENB | input | Side B output enable, active high or floating (internally pulled up to VDDB); low puts outputs VO1-VO4 in high impedance. |
| 11 | VO4 | output | Side B logic output for channel 4 on CA-IS3740 (tri-state via ENB). |
| 12 | VO3 | output | Side B logic output for channel 3 on CA-IS3740 (tri-state via ENB). |
| 13 | VO2 | output | Side B logic output for channel 2 (tri-state via ENB). |
| 14 | VO1 | output | Side B logic output for channel 1 (tri-state via ENB). |
| 15 | GNDB | power_in | Side B ground reference. |
| 16 | VDDB | power_in | Side B supply voltage, recommended 2.375 V to 5.5 V with a 0.1 µF to 1 µF bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDDA, VDDB | -0.5 | 7 | V | 5 | ||
| Input voltage Ax, Bx, ENx | Vin | -0.5 | V | max VDD+0.5, not to exceed 7 V | 5 | ||
| Output current | IO | -20 | 20 | mA | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature | TSTG | -65 | 150 | °C | 5 | ||
| ESD HBM | VESD | -6000 | 6000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| ESD CDM | VESD | -2000 | 2000 | V | JESD22-C101, all pins | 5 | |
| Supply voltage | VDDA, VDDB | 2.375 | 5.5 | V | typ 3.3/5.0 | 5 | |
| UVLO rising threshold | VDD(UVLO+) | 1.95 | 2.24 | 2.37 | V | 5 | |
| UVLO falling threshold | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | 5 | |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level output current | IOH | -4 | mA | VDDO = 5V (-2 at 3.3V, -1 at 2.5V) | 5 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5V (2 at 3.3V, 1 at 2.5V) | 5 | ||
| Input logic high threshold | VIH | 2 | V | 5 | |||
| Input logic low threshold | VIL | 0.8 | V | 5 | |||
| Signal rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 83.4 | °C/W | SOIC16-WB(W) | 6 | ||
| Maximum power dissipation | PD | 334 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave | 6 | ||
| Side A max power dissipation | PDA | 36 | mW | same as PD | 6 | ||
| Side B max power dissipation | PDB | 298 | mW | same as PD | 6 | ||
| Output high voltage | VOH | -0.4 | 4.8 | V | VDD=5V±10%, IOH = -4mA; min is VDDO-0.4 | 9 | |
| Output low voltage | VOL | 0.2 | 0.4 | V | VDD=5V±10%, IOL = 4mA | 9 | |
| Input threshold logic high | VIT+(IN) | 2 | V | 9 | |||
| Input threshold logic low | VIT-(IN) | 0.8 | V | 9 | |||
| Input high leakage current | IIH | 20 | µA | VIH = VDDA at Ax or Bx or ENx | 9 | ||
| Input low leakage current | IIL | -20 | µA | VIL = 0 V at Ax or Bx or ENx | 9 | ||
| Output impedance | ZO | 50 | Ω | 9 | |||
| Common-mode transient immunity | CMTI | 100 | 150 | kV/µs | VI = VDDI or 0 V, VCM = 1200 V | 9 | |
| Input capacitance | CI | 2 | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 9 | ||
| Output high voltage | VOH | -0.4 | 3.1 | V | VDD=3.3V±10%, IOH = -2mA; min is VDDO-0.4 | 9 | |
| Output high voltage | VOH | -0.4 | 2.3 | V | VDD=2.5V±5%, IOH = -1mA; min is VDDO-0.4 | 9 | |
| Supply current IDDA, DC high-side input | IDDA | 1.3 | 2.1 | mA | 5V; ENB = VDDB; VIN = VDDA (CA-IS3740H) | 10 | |
| Supply current IDDB, DC | IDDB | 2.7 | 3.9 | mA | 5V; ENB = VDDB; VIN = VDDA (CA-IS3740H) | 10 | |
| Supply current IDDA, DC input low | IDDA | 6.4 | 9.5 | mA | 5V; ENB = VDDB; VIN = 0V (CA-IS3740H) | 10 | |
| Supply current IDDB, DC input low | IDDB | 2.7 | 4 | mA | 5V; ENB = VDDB; VIN = 0V (CA-IS3740H) | 10 | |
| Supply current IDDA, 1Mbps | IDDA | 3.9 | 5.8 | mA | 5V; ENB = VDDB; 500kHz square wave, CL = 15 pF | 10 | |
| Supply current IDDB, 1Mbps | IDDB | 4.4 | 6.1 | mA | 5V; ENB = VDDB; 500kHz square wave, CL = 15 pF | 10 | |
| Supply current IDDB, 10Mbps | IDDB | 18.7 | 24.8 | mA | 5V; ENB = VDDB; 5MHz square wave, CL = 15 pF | 10 | |
| Supply current IDDA, 100Mbps | IDDA | 4.7 | 6.8 | mA | 5V; ENB = VDDB; 50MHz square wave, CL = 15 pF | 10 | |
| Supply current IDDB, 100Mbps | IDDB | 41 | 54.7 | mA | 5V; ENB = VDDB; 50MHz square wave, CL = 15 pF | 10 | |
| Data rate | DR | 150 | Mbps | VDD = 5V±10% | 13 | ||
| Minimum pulse width | PWmin | 5 | ns | VDD = 5V±10% | 13 | ||
| Propagation delay | tPLH, tPHL | 5 | 12 | 16 | ns | Figure 8-1, VDD = 5V±10% | 13 |
| Pulse width distortion | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/, VDD = 5V±10% | 13 | |
| Channel-to-channel output skew | tsk(o) | 0.4 | 2.5 | ns | same-direction channels | 13 | |
| Part-to-part skew | tsk(pp) | 2 | 4.5 | ns | VDD = 5V±10% | 13 | |
| Output rise time | tr | 2.5 | 4 | ns | Figure 8-1 | 13 | |
| Output fall time | tf | 2.5 | 4 | ns | Figure 8-1 | 13 | |
| Disable delay, high to Hi-Z | tPHZ | 8 | 13 | ns | Figure 8-2, 5V | 13 | |
| Disable delay, low to Hi-Z | tPLZ | 8 | 17 | ns | Figure 8-2, 5V | 13 | |
| Enable delay, Hi-Z to high | tPZH | 15 | 30 | ns | CA-IS374xH, 5V | 13 | |
| Enable delay, Hi-Z to low | tPZL | 15 | 30 | ns | CA-IS374xH, 5V | 13 | |
| Default output delay | tDO | 8 | 12 | µs | Figure 8-3 | 13 | |
| Start-up time | tSU | 15 | 40 | µs | 13 | ||
| Isolation rating | VISO | 5000 | VRMS | UL 1577, t = 60 s, SOIC16-WB | 7 | ||
| Barrier capacitance | CIO | 0.5 | pF | VIO = 0.4 × sin (2πft), f = 1 MHz | 7 |
CAD (KiCad official)
- Symbol:
CA-IS3740HW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is3740hw-etched.step/ca-is3740hw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3740hw.step/ca-is3740hw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
fd7bb5373a55db4c, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).