component
CA-IS3740HN
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IS3740HN
Chipanalog · Digital Isolators · SOIC-16
CA-IS3740HN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A supply voltage, recommended 2.375 V to 5.5 V, with a 0.1 µF to 1 µF bypass capacitor to GNDA. |
| 2 | GNDA | power_in | Side A ground reference. |
| 3 | VI1 | input | Side A logic input, channel 1. |
| 4 | VI2 | input | Side A logic input, channel 2. |
| 5 | VI3 | input | Side A logic input, channel 3 (CA-IS3740). |
| 6 | VI4 | input | Side A logic input, channel 4 (CA-IS3740). |
| 7 | NC | unconnected | No internal connection on CA-IS3740; may be left floating or connected to VDD or GND. |
| 8 | GNDA | power_in | Side A ground reference. |
| 9 | GNDB | power_in | Side B ground reference. |
| 10 | ENB | input | Side B output enable, active high or floating, internally pulled up to VDDB; low puts outputs VO1 to VO4 in high impedance. |
| 11 | VO4 | output | Side B logic output, channel 4 (CA-IS3740), high-Z when ENB is low. |
| 12 | VO3 | output | Side B logic output, channel 3 (CA-IS3740), high-Z when ENB is low. |
| 13 | VO2 | output | Side B logic output, channel 2, high-Z when ENB is low. |
| 14 | VO1 | output | Side B logic output, channel 1, high-Z when ENB is low. |
| 15 | GNDB | power_in | Side B ground reference. |
| 16 | VDDB | power_in | Side B supply voltage, recommended 2.375 V to 5.5 V, with a 0.1 µF to 1 µF bypass capacitor to GNDB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16 |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB (absolute max) | VDDA, VDDB | -0.5 | 7 | V | 5 | ||
| Input voltage Ax, Bx, ENx (absolute max) | Vin | -0.5 | V | VDD+0.5, max voltage not to exceed 7 V | 5 | ||
| Output current (absolute max) | IO | -20 | 20 | mA | 5 | ||
| Junction temperature (absolute max) | TJ | 150 | °C | 5 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| ESD HBM | VESD | -6000 | 6000 | V | HBM per ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| ESD CDM | VESD | -2000 | 2000 | V | CDM per JESD22-C101, all pins | 5 | |
| Supply voltage VDDA, VDDB | VDDA, VDDB | 2.375 | 5.5 | V | typ 3.3/5.0 | 5 | |
| UVLO rising threshold | VDD(UVLO+) | 1.95 | 2.24 | 2.37 | V | VDD rising | 5 |
| UVLO falling threshold | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | VDD falling | 5 |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level output current | IOH | -4 | mA | VDDO = 5V (-2 at 3.3V, -1 at 2.5V) | 5 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5V (2 at 3.3V, 1 at 2.5V) | 5 | ||
| Input threshold logic high | VIH | 2 | V | 5 | |||
| Input threshold logic low | VIL | 0.8 | V | 5 | |||
| Signaling rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Junction-to-ambient thermal resistance SOIC16-NB | RθJA | 96.2 | °C/W | SOIC16-NB (N) | 6 | ||
| Maximum power dissipation CA-IS3740 | PD | 334 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave | 6 | ||
| Max power dissipation side A | PDA | 36 | mW | 6 | |||
| Max power dissipation side B | PDB | 298 | mW | 6 | |||
| High-level output voltage | VOH | 4.8 | V | VDD=5V±10%, IOH = -4mA; min is VDDO-0.4 | 9 | ||
| Low-level output voltage | VOL | 0.2 | 0.4 | V | VDD=5V±10%, IOL = 4mA | 9 | |
| Input threshold logic high | VIT+(IN) | 2 | V | VDD=5V±10% | 9 | ||
| Input threshold logic low | VIT-(IN) | 0.8 | V | VDD=5V±10% | 9 | ||
| Input high leakage current | IIH | 20 | µA | VIH = VDDA at Ax or Bx or ENx | 9 | ||
| Input low leakage current | IIL | -20 | µA | VIL = 0 V at Ax or Bx or ENx | 9 | ||
| Output impedance | ZO | 50 | Ω | 9 | |||
| Common-mode transient immunity | CMTI | 100 | 150 | kV/µs | VI = VDDI or 0 V, VCM = 1200 V | 9 | |
| Input capacitance | CI | 2 | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 9 | ||
| Supply current IDDA, DC, input high (H) | IDDA | 1.3 | 2.1 | mA | VDD=5V, ENB = VDDB; VIN = VDDA (CA-IS3740H) | 10 | |
| Supply current IDDB, DC, input high (H) | IDDB | 2.7 | 3.9 | mA | VDD=5V, ENB = VDDB; VIN = VDDA (CA-IS3740H) | 10 | |
| Supply current IDDA, DC, input low (H) | IDDA | 6.4 | 9.5 | mA | VDD=5V, ENB = VDDB; VIN = 0V (CA-IS3740H) | 10 | |
| Supply current IDDB, DC, input low (H) | IDDB | 2.7 | 4 | mA | VDD=5V, ENB = VDDB; VIN = 0V (CA-IS3740H) | 10 | |
| Supply current IDDA, 100Mbps | IDDA | 4.7 | 6.8 | mA | VDD=5V, ENB = VDDB; 50 MHz square wave, CL = 15 pF | 10 | |
| Supply current IDDB, 100Mbps | IDDB | 41 | 54.7 | mA | VDD=5V, ENB = VDDB; 50 MHz square wave, CL = 15 pF | 10 | |
| Data rate | DR | 150 | Mbps | 13 | |||
| Minimum pulse width | PWmin | 5 | ns | 13 | |||
| Propagation delay | tPLH, tPHL | 5 | 12 | 16 | ns | Figure 8-1 | 13 |
| Pulse width distortion | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 13 | |
| Channel-to-channel skew | tsk(o) | 0.4 | 2.5 | ns | same-direction channels | 13 | |
| Part-to-part skew | tsk(pp) | 2 | 4.5 | ns | 13 | ||
| Output rise time | tr | 2.5 | 4 | ns | Figure 8-1 | 13 | |
| Output fall time | tf | 2.5 | 4 | ns | Figure 8-1 | 13 | |
| Disable delay, high to Hi-Z | tPHZ | 8 | 13 | ns | Figure 8-2 | 13 | |
| Disable delay, low to Hi-Z | tPLZ | 8 | 17 | ns | Figure 8-2 | 13 | |
| Enable delay, Hi-Z to high | tPZH | 15 | 30 | ns | CA-IS374xH, Figure 8-2 | 13 | |
| Enable delay, Hi-Z to low | tPZL | 15 | 30 | ns | CA-IS374xH, Figure 8-2 | 13 | |
| Default output delay time | tDO | 8 | 12 | µs | from UVLO, Figure 8-3 | 13 | |
| Start-up time | tSU | 15 | 40 | µs | 13 | ||
| Maximum isolation voltage (UL 1577) | VISO | 3750 | VRMS | SOIC16-NB, VTEST = VISO, t = 60 s | 7 |
CAD (KiCad official)
- Symbol:
CA-IS3740HN - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
ca-is3740hn-etched.step/ca-is3740hn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3740hn.step/ca-is3740hn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
fd7bb5373a55db4c, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).