CA-IS3731LW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDDA	power_in	A-side supply voltage; recommended range is 2.375 V to 5.5 V (typical 3.3 V), with a 0.1 µF to 1 µF bypass capacitor per the application note.
2	GNDA	power_in	A-side ground reference point for the isolated input-side circuitry.
3	VI1	input	A-side logic input for channel 1 (forward channel, A to B).
4	VI2	input	A-side logic input for channel 2 (forward channel, A to B).
5	VO3	output	On CA-IS3731 this pin is the A-side logic output of the reverse channel (B to A); the same physical pin is VI3/VO3 on the CA-IS3730.
6	NC	unconnected	No internal connection; may be left floating, tied to VDD, or tied to GND.
7	ENA	input	A-side enable input, active high, internally pulled up to the local VDD; leave floating or connect to a defined logic level, and avoid routing traces to it when floating in noisy environments.
8	GNDA	power_in	A-side ground reference point for the isolated input-side circuitry.
9	GNDB	power_in	B-side ground reference point for the isolated output-side circuitry.
10	ENB	input	B-side enable input, active high, internally pulled up to the local VDD; when low the B-side outputs go to high impedance.
11	NC	unconnected	No internal connection; may be left floating, tied to VDD, or tied to GND.
12	VI3	input	On CA-IS3731 this pin is the B-side logic input of the reverse channel (B to A); the same physical pin is VI3/VO3 on the CA-IS3730.
13	VO2	output	B-side logic output for channel 2 (forward channel, A to B), tri-state controlled by ENB.
14	VO1	output	B-side logic output for channel 1 (forward channel, A to B), tri-state controlled by ENB.
15	GNDB	power_in	B-side ground reference point for the isolated output-side circuitry.
16	VDDB	power_in	B-side supply voltage; recommended range is 2.375 V to 5.5 V (typical 3.3 V), with a 0.1 µF to 1 µF bypass capacitor per the application note.

Key specifications

Parameter	Value
Manufacturer	Chipanalog
Package	SOIC-16-300mil
Category	Interface ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VDDA, VDDB	-0.5		6	V		5
Input voltage (Ax, Bx, ENx)	Vin	-0.5			V	max printed as VDDA+0.5 (note 3: must not exceed 6 V)	5
Output current	IO	-20		20	mA		5
Junction temperature	TJ			150	°C		5
Storage temperature range	TSTG	-65		150	°C		5
Supply voltage	VDDA, VDDB	2.375	3.3	5.5	V		5
UVLO threshold, supply rising	VDD(UVLO+)	1.95	2.24	2.375	V	VDD rising	5
UVLO threshold, supply falling	VDD(UVLO-)	1.88	2.1	2.325	V	VDD falling	5
UVLO hysteresis	VHYS(UVLO)	70	140	250	mV		5
High-level output current	IOH			-4	mA	VDDO1 = 5V	5
High-level output current	IOH			-2	mA	VDDO = 3.3V	5
High-level output current	IOH			-1	mA	VDDO = 2.5V	5
Low-level output current	IOL			4	mA	VDDO = 5V	5
Low-level output current	IOL			2	mA	VDDO = 3.3V	5
Low-level output current	IOL			1	mA	VDDO = 2.5V	5
Input threshold logic high	VIH	2			V		5
Input threshold logic low	VIL			0.8	V		5
Signaling data rate	DR	0		150	Mbps		5
Ambient temperature	TA	-40	27	125	°C		5
Maximum power dissipation	PD			252	mW	VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, input 75MHz 50% duty square wave	6
Maximum isolation voltage (certification)	VISO			5000	VRMS	VTEST = VISO, t = 60 s (certification)	7
Maximum transient isolation voltage	VIOTM			7070	VPK	VTEST = VIOTM, t = 60 s (certification)	7
Output voltage logic low	VOL		0.2	0.4	V	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; IOL = 4mA; 图 7-2	9
Positive input threshold	VIT+(IN)	1.4	1.67	1.9	V	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C	9
Negative input threshold	VIT-(IN)	1	1.23	1.4	V	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C	9
Input threshold hysteresis	VI(HYS)	0.3	0.44	0.5	V	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C	9
Input high-level leakage current	IIH			4	µA	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; VIH = VDDA at Ax or Bx or ENx	9
Input low-level leakage current	IIL	-4			µA	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; VIL = 0 V at Ax or Bx	9
Common-mode transient immunity	CMTI	75	100		kV/µs	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; VI = VDDI1 or 0 V, VCM = 1200 V; 图 7-4	9
Output impedance tolerance	ZO	-40		40	%	normal isolator channel output impedance, about 50 Ω (note 2)	9
Minimum pulse width	PWmin	5			ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C	13
Propagation delay	tPLH, tPHL	5	8	13	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; 图 7-1	13
Pulse width distortion	PWD		0.2	4.5	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; /tPLH - tPHL/	13
Channel-to-channel output skew, same direction	tsk(o)		0.4	2.5	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; same-direction channels (note 1)	13
Part-to-part output skew	tsk(pp)		2	4.5	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; note 2	13
Output rise time	tr		2.5	4	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; 图 7-1	13
Output fall time	tf		2.5	4	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; 图 7-1	13
Disable propagation delay, output high to high-Z	tPHZ		8	12	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; 图 7-2	13
Disable propagation delay, output low to high-Z	tPLZ		8	12	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; 图 7-2	13
Enable propagation delay, high-Z to high (CA-IS373xL)	tPZH		10	20	ns	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; CA-IS373xL	13
Enable propagation delay, high-Z to low (CA-IS373xL)	tPZL		5	10	µs	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; CA-IS373xL	13
Default output delay time from input power loss	tDO		0.1	0.3	µs	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C; 图 7-3	13
Start-up time	tSU		15	40	µs	VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C	13
Supply current, side A, enable off, VIN = 0 V	IDDA		1.4	2.1	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = 0 V; VIN = 0V (CA-IS3731L)	10
Supply current, side B, enable off, VIN = 0 V	IDDB		1.8	2.7	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = 0 V; VIN = 0V (CA-IS3731L)	10
Supply current, side A, enable off, VIN = VDDI	IDDA		2.9	4.5	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = 0 V; VIN = VDDI (CA-IS3731L)	10
Supply current, side B, enable off, VIN = VDDI	IDDB		2.6	3.9	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = 0 V; VIN = VDDI (CA-IS3731L)	10
Supply current, side A, DC signal, VIN = 0 V	IDDA		1.5	2.2	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = VDDI; VIN = 0V (CA-IS3731L)	10
Supply current, side B, DC signal, VIN = 0 V	IDDB		2	2.9	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = VDDI; VIN = 0V (CA-IS3731L)	10
Supply current, side A, DC signal, VIN = VDDI	IDDA		3	4.5	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = VDDI; VIN = VDDI (CA-IS3731L)	10
Supply current, side B, DC signal, VIN = VDDI	IDDB		2.8	4.2	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = VDDI; VIN = VDDI (CA-IS3731L)	10
Supply current, side A, 1 Mbps	IDDA		2.3	3.4	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = VDDI; all channels 50% duty 5 V square wave, CL = 15 pF, 1Mbps (500kHz) (CA-IS3731L)	10
Supply current, side B, 1 Mbps	IDDB		2.5	3.7	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = VDDI; all channels 50% duty 5 V square wave, CL = 15 pF, 1Mbps (500kHz) (CA-IS3731L)	10
Supply current, side A, 100 Mbps	IDDA		7.5	11.3	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = VDDI; all channels 50% duty 5 V square wave, CL = 15 pF, 100Mbps (50MHz) (CA-IS3731L)	10
Supply current, side B, 100 Mbps	IDDB		12.9	19.4	mA	VDDA = VDDB = 5 V ± 10%; ENA = ENB = VDDI; all channels 50% duty 5 V square wave, CL = 15 pF, 100Mbps (50MHz) (CA-IS3731L)	10
Junction-to-ambient thermal resistance	RθJA		83.4		°C/W	SOIC16-WB (W)	6
Junction-to-case (top) thermal resistance	RθJC(top)		46		°C/W	SOIC16-WB (W)	6
Junction-to-board thermal resistance	RθJB		48		°C/W	SOIC16-WB (W)	6
Junction-to-top characterization parameter	ψJT		19.1		°C/W	SOIC16-WB (W)	6
Junction-to-board characterization parameter	ψJB		47.5		°C/W	SOIC16-WB (W)	6

CAD (KiCad official)

Symbol: CA-IS3731LW
Footprint: Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm
3D model: SOIC-16-300mil (KiCad packages3D, STEP)
3D model files: ca-is3731lw-etched.step / ca-is3731lw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3731lw.step / ca-is3731lw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Chipanalog datasheet (23 pp, sha256 27de2cc191feda49, retrieved 2026-11-12, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CA-IS3731LW

Verified CA-IS3731LW

Verification log 1 record

3D Model

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Datasheet

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