component

CA-IS3731LN

Public Made by Adom

by adom

Chipanalog Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsca-is3731lnfactory-2.0.0extractor-text

Verified CA-IS3731LN

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CA-IS3731LN · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 19-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_22xnzdq/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.19)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ca-is3731ln.kicad_sym✓ ca-is3731ln.kicad_mod✓ ca-is3731ln.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 9d ago
viewers ca-is3731ln: viewers · Ray 9d ago
ca-is3731ln-etched.glb Publish 0.1.0 · Ray 9d ago
ca-is3731ln-etched.step ca-is3731ln: factory component page (tier=lcsc) · Ray 9d ago
ca-is3731ln-hero.glb ca-is3731ln: hero GLB from the etched model (keeps the MPN mark) · Ray 9d ago
ca-is3731ln-hero.overlay.json Publish 0.1.0 · Ray 9d ago
ca-is3731ln.glb Publish 0.1.0 · Ray 9d ago
ca-is3731ln.kicad_mod Publish 0.1.0 · Ray 9d ago
ca-is3731ln.kicad_sym Publish 0.1.0 · Ray 9d ago
ca-is3731ln.lbr Publish 0.1.0 · Ray 9d ago
ca-is3731ln.step Publish 0.1.0 · Ray 9d ago
package.json Publish 0.1.0 · Ray 9d ago
page.json Set visibility: public · Ray 9d ago
README.md Publish 0.1.0 · Ray 9d ago
verification.json Verified: Published by the parts factory: tier lcsc, 16 pins · Ray 9d ago

CA-IS3731LN

Chipanalog · Digital Isolators · SOIC-16

CA-IS3731LN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A power supply, 2.375 V to 5.5 V recommended, with a 0.1 µF to 1 µF bypass capacitor.
2 GNDA power_in Side A ground.
3 A1 input Side A digital input (channel 1, isolated to B1).
4 A2 input Side A digital input (channel 2, isolated to B2).
5 A3 output Side A digital output for CA-IS3731 (reverse channel from B3); tri-stated when ENA is low.
6 NC unconnected No connect; not internally connected, can be left floating, tied to VDD or tied to GND.
7 ENA input Side A active-high enable, internally pulled up to VDDA; low puts output A3 in high impedance.
8 GNDA power_in Side A ground.
9 GNDB power_in Side B ground.
10 ENB input Side B active-high enable, internally pulled up to VDDB; low puts outputs B1, B2 in high impedance.
11 NC unconnected No connect; not internally connected, can be left floating, tied to VDD or tied to GND.
12 B3 input Side B digital input for CA-IS3731 (channel 3, isolated to A3).
13 B2 output Side B digital output.
14 B1 output Side B digital output.
15 GNDB power_in Side B ground.
16 VDDB power_in Side B power supply, 2.375 V to 5.5 V recommended, with a 0.1 µF to 1 µF bypass capacitor.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDA, VDDB 2.375 3.3 5.5 V 5
VDD Undervoltage Threshold Rising VDD(UVLO+) 1.95 2.24 2.375 V 5
VDD Undervoltage Threshold Falling VDD(UVLO-) 1.88 2.16 2.325 V 5
UVLO Hysteresis VHYS(UVLO) 50 70 95 mV 5
High-level Output Current IOH -4 mA VDDO = 5V 5
High-level Output Current IOH -2 mA VDDO = 3.3V 5
High-level Output Current IOH -1 mA VDDO = 2.5V 5
Low-level Output Current IOL 4 mA VDDO = 5V 5
Low-level Output Current IOL 2 mA VDDO = 3.3V 5
High-level Input Voltage VIH 2 V 5
Low-level Input Voltage VIL 0.8 V 5
Data Rate DR 0 150 Mbps 5
Ambient Temperature TA -40 27 125 °C 5
Supply Voltage VDDA, VDDB -0.5 6 V 5
Voltage at Ax, Bx, ENx Vin -0.5 6 V VDDA+0.5, must not exceed 6 V 5
Output Current IO 15 15 mA 5
Junction Temperature TJ 150 °C 5
Storage Temperature TSTG -65 150 °C 5
ESD HBM VESD 2000 V HBM, all pins 5
ESD CDM VESD 200 V CDM, all pins 5
Max Power Dissipation PD 150 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75-MHz 50% duty cycle square wave 6
Max Power Dissipation Side-A PDA 50 mW CA-IS3731 6
Max Power Dissipation Side-B PDB 100 mW CA-IS3731 6
High-level Output Voltage VOH 4.8 V VDD=5V; IOH = -4mA; min is VDDO-0.4 7
Low-level Output Voltage VOL 0.2 0.4 V IOL = 4mA 7
Positive-going Input Threshold VIT+(IN) 1.4 1.67 1.9 V 7
Negative-going Input Threshold VIT-(IN) 1 1.23 1.4 V 7
Input Threshold Hysteresis VI(HYS) 0.38 0.44 0.5 V 7
High-Level Input Leakage Current IIH 10 µA VIH = VDDA at Ax or Bx or ENx 7
Low-Level Input Leakage Current IIL -10 µA VIL = 0 V at Ax or Bx 7
Common-mode Transient Immunity CMTI 85 100 kV/µs VI = VDDI or 0 V, VCM = 1200 V 7
Input Capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 3.3 V 7
Supply Current IDDA Disable (low-input case) IDDA 1.3 2.1 mA CA-IS3731, ENA = ENB = 0 V; VIN = 0V (L) 9
Supply Current IDDB Disable (low-input case) IDDB 1.7 2.7 mA CA-IS3731, ENA = ENB = 0 V; VIN = 0V (L) 9
Supply Current IDDA 100Mbps IDDA 5 7 mA CA-IS3731, 3.3V, 100Mbps (50MHz), CL = 15 pF 9
Supply Current IDDB 100Mbps IDDB 7.3 9.8 mA CA-IS3731, 3.3V, 100Mbps (50MHz), CL = 15 pF 9
Data Rate DR 0 150 Mbps 11
Minimum Pulse Width PWmin 5 ns 11
Propagation Delay Time tPLH, tPHL 5 8 13 ns See Figure 8-1 11
Pulse Width Distortion PWD 0.2 4.5 ns /tPLH - tPHL/ 11
Channel-to-channel Output Skew tsk(o) 0.4 2.5 ns Same-direction channels 11
Part-to-part Skew tsk(pp) 2 4.5 ns See Figure 8-1 11
Output Signal Rise Time tr 2.5 4 ns See Figure 8-1 11
Output Signal Fall Time tf 2.5 4 ns See Figure 8-1 11
Disable Propagation Delay, High to High Impedance tPHZ 8 12 ns See Figure 8-2 11
Disable Propagation Delay, Low to High Impedance tPLZ 8 12 ns See Figure 8-2 11
Enable Propagation Delay, High Impedance to High Output tPZH 6 11 ns CA-IS373xL 11
Default Output Delay Time from Input Power Loss tDO 8 12 ns See Figure 8-3 11
Start-up Time tSU 15 40 µs 11

CAD (KiCad official)

  • Symbol: CA-IS3731LN
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ca-is3731ln-etched.step / ca-is3731ln-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3731ln.step / ca-is3731ln.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (19 pp, sha256 ef3209513577c58b, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF