component

CA-IS3730LN

Public Made by Adom

by adom

Chipanalog Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentisolatorsca-is3730lnfactory-2.0.0extractor-text

Verified CA-IS3730LN

by Ray · last 4 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

4 Nov 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CA-IS3730LN · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 25-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-noeitooh/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ca-is3730ln.kicad_sym✓ ca-is3730ln.kicad_mod✓ ca-is3730ln.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers ca-is3730ln: viewers · Ray
ca-is3730ln-etched.glb Publish 0.1.0 · Ray
ca-is3730ln-etched.step ca-is3730ln: factory component page (tier=lcsc) · Ray
ca-is3730ln-hero.glb ca-is3730ln: hero GLB from the etched model (keeps the MPN mark) · Ray
ca-is3730ln-hero.overlay.json Publish 0.1.0 · Ray
ca-is3730ln.glb Publish 0.1.0 · Ray
ca-is3730ln.kicad_mod Publish 0.1.0 · Ray
ca-is3730ln.kicad_sym Publish 0.1.0 · Ray
ca-is3730ln.lbr Publish 0.1.0 · Ray
ca-is3730ln.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 16 pins · Ray

CA-IS3730LN

Chipanalog · Digital Isolators · SOIC-16

CA-IS3730LN from Chipanalog, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage, recommended operating range 2.375 V to 5.5 V.
2 GNDA power_in Side A ground reference for the A-side signals and supply.
3 VI1 input Side A logic input channel 1, Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
4 VI2 input Side A logic input channel 2, Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
5 VI3 input Side A logic input channel 3 on CA-IS3730 (VO3 logic output on CA-IS3731), Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
6 NC unconnected No internal connection; may be left floating or tied to VDD or GND.
7 NC unconnected No internal connection on CA-IS3730 (ENA enable input on CA-IS3731); may be left floating or tied to VDD or GND.
8 GNDA power_in Side A ground reference for the A-side signals and supply.
9 GNDB power_in Side B ground reference for the B-side signals and supply.
10 ENB input Side B output enable, active high or floating; internally pulled up to local VDD, and a low level puts the B-side outputs in high impedance.
11 NC unconnected No internal connection; may be left floating or tied to VDD or GND.
12 VO3 output Side B logic output channel 3 on CA-IS3730 (VI3 logic input on CA-IS3731).
13 VO2 output Side B logic output channel 2, with VOH minimum 4.8 V at 5 V supply and VOL maximum 0.4 V at IOL 4 mA.
14 VO1 output Side B logic output channel 1, with VOH minimum 4.8 V at 5 V supply and VOL maximum 0.4 V at IOL 4 mA.
15 GNDB power_in Side B ground reference for the B-side signals and supply.
16 VDDB power_in Side B supply voltage, recommended operating range 2.375 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16
Category Isolators
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDDA, VDDB power supply voltage VDDA, VDDB 2.375 3.3 5.5 V 5
VDD undervoltage threshold, rising VDD(UVLO+) 1.95 2.24 2.375 V VDD rising 5
VDD undervoltage threshold, falling VDD(UVLO-) 1.88 2.1 2.325 V VDD falling 5
VDD UVLO hysteresis VHYS(UVLO) 70 140 250 mV 5
High-level output current, VDDO = 5 V IOH -4 mA VDDO = 5 V 5
High-level output current, VDDO = 3.3 V IOH -2 mA VDDO = 3.3 V 5
High-level output current, VDDO = 2.5 V IOH -1 mA VDDO = 2.5 V 5
Low-level output current, VDDO = 5 V IOL 4 mA VDDO = 5 V 5
Low-level output current, VDDO = 3.3 V IOL 2 mA VDDO = 3.3 V 5
Low-level output current, VDDO = 2.5 V IOL 1 mA VDDO = 2.5 V 5
Input threshold logic high VIH 2 V 5
Input threshold logic low VIL 0.8 V 5
Signaling data rate DR 0 150 Mbps 5
Ambient temperature TA -40 27 125 °C 5
Supply voltage VDDA, VDDB (absolute) VDDA, VDDB -0.5 7 V 5
Input voltage Ax, Bx, ENx (max printed as VDD+0.5 V) Vin -0.5 V 5
Output current IO -20 20 mA 5
Junction temperature TJ 150 °C 5
Storage temperature range TSTG -65 150 °C 5
ESD human body model (HBM) VESD -6000 6000 V ANSI/ESDA/JEDEC JS-001, all pins 5
ESD charged device model (CDM) VESD -2000 2000 V JEDEC JESD22-C101, all pins 5
Junction-to-ambient thermal resistance, SOIC16-NB RθJA 96.2 °C/W SOIC16-NB (N) package 6
Maximum power dissipation, total PD 252 mW VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75 MHz 50% duty square input 6
Maximum power dissipation, side A PDA 27 mW 6
Maximum power dissipation, side B PDB 225 mW 6
Logic high output voltage VOH 4.8 V IOH = -4 mA; Fig 8-2 9
Logic low output voltage VOL 0.2 0.4 V IOL = 4 mA; Fig 8-2 9
Input threshold logic high (5 V) VIT+(IN) 2 V 9
Input threshold logic low (5 V) VIT-(IN) 0.8 V 9
Input high-level leakage current IIH 20 µA VIH = VDDA at Ax or Bx or ENx 9
Input low-level leakage current IIL -20 µA VIL = 0 V at Ax or Bx 9
Output impedance ZO 50 Ω 9
Common-mode transient immunity CMTI 100 150 kV/µs VI = VDDI or 0 V, VCM = 1200 V; Fig 8-4 9
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V 9
Minimum pulse width PWmin 5 ns 13
Propagation delay tPLH, tPHL 5 12 15 ns Fig 8-1 13
Pulse width distortion PWD 0.2 4.5 ns /tPLH - tPHL/ 13
Channel-to-channel output skew, same direction tsk(o) 0.4 2.5 ns Same-direction channels, same device (note 1) 13
Part-to-part channel output skew tsk(pp) 2 4 ns Part-to-part (note 2) 13
Output rise time tr 2.5 4 ns Fig 8-1 13
Output fall time tf 2.5 4 ns Fig 8-1 13
Disable propagation delay, output high to high-Z tPHZ 8 13 ns Fig 8-2 13
Disable propagation delay, output low to high-Z tPLZ 8 17 ns Fig 8-2 13
Enable propagation delay, high-Z to high (CA-IS373xL) tPZH 10 20 ns CA-IS373xL; Fig 8-2 13
Enable propagation delay, high-Z to low (CA-IS373xL) tPZL 10 25 ns CA-IS373xL; Fig 8-2 13
Default output delay from input supply UVLO tDO 0.1 0.3 µs Fig 8-3 13
Startup time tSU 15 40 µs 13
Supply current IDDA, enable-off (CA-IS3730L input 0 V) IDDA 1.2 2.6 mA ENB = 0 V; VIN = 0 V (CA-IS3730L) 10
Supply current IDDB, enable-off (CA-IS3730L input 0 V) IDDB 2.1 3.8 mA ENB = 0 V; VIN = 0 V (CA-IS3730L) 10
Supply current IDDA, enable-off (CA-IS3730L input VDDA) IDDA 5 7.7 mA ENB = 0 V; VIN = VDDA (CA-IS3730L) 10
Supply current IDDB, enable-off (CA-IS3730L input VDDA) IDDB 1.9 3.6 mA ENB = 0 V; VIN = VDDA (CA-IS3730L) 10
Supply current IDDA, AC 1 Mbps IDDA 2.2 4.5 mA ENB = VDDB; all inputs 50% duty 5 V square wave; CL = 15 pF per channel; 1 Mbps (500 kHz) 10
Supply current IDDB, AC 1 Mbps IDDB 2.4 5.4 mA ENB = VDDB; all inputs 50% duty 5 V square wave; CL = 15 pF per channel; 1 Mbps (500 kHz) 10
Supply current IDDA, AC 10 Mbps IDDA 2.2 4.5 mA ENB = VDDB; all inputs 50% duty 5 V square wave; CL = 15 pF per channel; 10 Mbps (5 MHz) 10
Supply current IDDB, AC 10 Mbps IDDB 3.9 8.8 mA ENB = VDDB; all inputs 50% duty 5 V square wave; CL = 15 pF per channel; 10 Mbps (5 MHz) 10
Supply current IDDA, AC 100 Mbps IDDA 2.2 4.5 mA ENB = VDDB; all inputs 50% duty 5 V square wave; CL = 15 pF per channel; 100 Mbps (50 MHz) 10
Supply current IDDB, AC 100 Mbps IDDB 18.1 42 mA ENB = VDDB; all inputs 50% duty 5 V square wave; CL = 15 pF per channel; 100 Mbps (50 MHz) 10

CAD (KiCad official)

  • Symbol: CA-IS3730LN
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ca-is3730ln-etched.step / ca-is3730ln-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3730ln.step / ca-is3730ln.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (25 pp, sha256 3334f70aba2bcfaf, retrieved 2026-11-04, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF