component
CA-IS3730HW
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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CA-IS3730HW
Chipanalog · Digital Isolators · SOIC-16-300mil
CA-IS3730HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side-A supply voltage, recommended range 2.375 V to 5.5 V, with a 1 µF bypass capacitor placed within 2 mm of the pin per the typical application circuit. |
| 2 | GNDA | power_in | Side-A ground reference point for the A-side supply and logic inputs. |
| 3 | VI1 | input | Side-A logic input, channel 1; Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V, TTL-compatible. |
| 4 | VI2 | input | Side-A logic input, channel 2; Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V, TTL-compatible. |
| 5 | VI3 | input | Side-A logic input, channel 3 on the CA-IS3730 (this pin is the side-A logic output VO3 on the CA-IS3731); Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V. |
| 6 | NC | unconnected | No internal connection; may be left floating, tied to VDD, or tied to GND. |
| 7 | NC | unconnected | Listed as NC1/ENA2 in the pin table; on the CA-IS3730 this pin has no internal connection, and the ENA enable function applies only to the CA-IS3731. |
| 8 | GNDA | power_in | Side-A ground reference point for the A-side supply and logic. |
| 9 | GNDB | power_in | Side-B ground reference point for the B-side supply and logic. |
| 10 | ENB | input | Side-B output enable, active high or floating; internally pulled up to local VDD, and a low level places the B-side outputs in high impedance, so tie to a defined logic level in noisy environments. |
| 11 | NC | unconnected | No internal connection; may be left floating, tied to VDD, or tied to GND. |
| 12 | VO3 | output | Side-B logic output, channel 3 on the CA-IS3730 (this pin is the side-B logic input VI3 on the CA-IS3731); outputs follow the input state when enabled and go high impedance when ENB is low. |
| 13 | VO2 | output | Side-B logic output, channel 2; typical output impedance about 50 Ω with rail-to-rail output swing. |
| 14 | VO1 | output | Side-B logic output, channel 1; typical output impedance about 50 Ω with rail-to-rail output swing. |
| 15 | GNDB | power_in | Side-B ground reference point for the B-side supply and logic. |
| 16 | VDDB | power_in | Side-B supply voltage, recommended range 2.375 V to 5.5 V, with a 1 µF bypass capacitor placed within 2 mm of the pin per the typical application circuit. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDDA, VDDB supply voltage (absolute maximum) | VDDA, VDDB | -0.5 | 7 | V | 5 | ||
| Output current | IO | -20 | 20 | mA | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| Input voltage Ax, Bx, ENx | Vin | -0.5 | V | Max printed as VDD+0.5 V; note 3: must not exceed 7 V | 5 | ||
| VDDA, VDDB supply voltage (recommended) | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | 5 | |
| VDD undervoltage threshold, rising (UVLO+) | VDD(UVLO+) | 1.95 | 2.24 | 2.375 | V | VDD rising | 5 |
| VDD undervoltage threshold, falling (UVLO-) | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | VDD falling | 5 |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level output current, VDDO = 5 V | IOH | -4 | mA | VDDO = 5 V | 5 | ||
| High-level output current, VDDO = 3.3 V | IOH | -2 | mA | VDDO = 3.3 V | 5 | ||
| High-level output current, VDDO = 2.5 V | IOH | -1 | mA | VDDO = 2.5 V | 5 | ||
| Low-level output current, VDDO = 5 V | IOL | 4 | mA | VDDO = 5 V | 5 | ||
| Low-level output current, VDDO = 3.3 V | IOL | 2 | mA | VDDO = 3.3 V | 5 | ||
| Low-level output current, VDDO = 2.5 V | IOL | 1 | mA | VDDO = 2.5 V | 5 | ||
| Input threshold logic high | VIH | 2 | V | 5 | |||
| Input threshold logic low | VIL | 0.8 | V | 5 | |||
| Signaling data rate (recommended) | DR | 0 | 150 | Mbps | 5 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Maximum power dissipation (CA-IS3730) | PD | 252 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, input 75MHz 50% duty square wave | 6 | ||
| Maximum power dissipation, side A (CA-IS3730) | PDA | 27 | mW | 6 | |||
| Maximum power dissipation, side B (CA-IS3730) | PDB | 225 | mW | 6 | |||
| Output voltage logic low | VOL | 0.2 | 0.4 | V | IOL = 4mA; 图 8-2 | 9 | |
| Input threshold logic high | VIT+(IN) | 2 | V | 9 | |||
| Input threshold logic low | VIT-(IN) | 0.8 | V | 9 | |||
| Input high-level leakage current | IIH | 20 | µA | VIH = VDDA at Ax or Bx or ENx | 9 | ||
| Input low-level leakage current | IIL | -20 | µA | VIL = 0 V at Ax or Bx | 9 | ||
| Common-mode transient immunity | CMTI | 100 | 150 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-4 | 9 | |
| Output impedance tolerance | ZO | -40 | 40 | % | 9 | ||
| Data rate | DR | 0 | 150 | Mbps | 13 | ||
| Minimum pulse width | PWmin | 5 | ns | 13 | |||
| Propagation delay | tPLH, tPHL | 5 | 12 | 15 | ns | 图 8-1 | 13 |
| Pulse width distortion | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 13 | |
| Channel-to-channel output skew, same direction | tsk(o) | 0.4 | 2.5 | ns | Same-direction channels | 13 | |
| Part-to-part channel output skew | tsk(pp) | 2 | 4 | ns | 13 | ||
| Output rise time | tr | 2.5 | 4 | ns | 图 8-1 | 13 | |
| Output fall time | tf | 2.5 | 4 | ns | 图 8-1 | 13 | |
| Disable propagation delay, output high to high-Z | tPHZ | 8 | 13 | ns | 图 8-2 | 13 | |
| Disable propagation delay, output low to high-Z | tPLZ | 8 | 17 | ns | 图 8-2 | 13 | |
| Enable propagation delay, output high-Z to high (CA-IS373xH) | tPZH | 15 | 30 | ns | CA-IS373xH; 图 8-2 | 13 | |
| Enable propagation delay, output high-Z to low (CA-IS373xH) | tPZL | 15 | 30 | ns | CA-IS373xH; 图 8-2 | 13 | |
| Default output delay from input supply UVLO | tDO | 0.1 | 0.3 | µs | 图 8-3 | 13 | |
| Startup time | tSU | 15 | 40 | µs | 13 | ||
| Supply current IDDA, enable off (CA-IS3730H, VIN = VDDA) | IDDA | 1.2 | 2.6 | mA | ENB = 0 V; VIN = VDDA (CA-IS3730H) | 10 | |
| Supply current IDDB, enable off (CA-IS3730H, VIN = VDDA) | IDDB | 2.1 | 3.8 | mA | ENB = 0 V; VIN = VDDA (CA-IS3730H) | 10 | |
| Supply current IDDA, enable off (CA-IS3730H, VIN = 0 V) | IDDA | 5 | 7.7 | mA | ENB = 0 V; VIN = 0V (CA-IS3730H) | 10 | |
| Supply current IDDB, enable off (CA-IS3730H, VIN = 0 V) | IDDB | 1.9 | 3.6 | mA | ENB = 0 V; VIN = 0V (CA-IS3730H) | 10 | |
| Supply current IDDA, DC signal (CA-IS3730H, VIN = VDDA) | IDDA | 1.2 | 2.6 | mA | ENB = VDDB; VIN = VDDA (CA-IS3730H) | 10 | |
| Supply current IDDB, DC signal (CA-IS3730H, VIN = VDDA) | IDDB | 2.1 | 3.8 | mA | ENB = VDDB; VIN = VDDA (CA-IS3730H) | 10 | |
| Supply current IDDA, DC signal (CA-IS3730H, VIN = 0 V) | IDDA | 5 | 7.7 | mA | ENB = VDDB; VIN = 0V (CA-IS3730H) | 10 | |
| Supply current IDDB, DC signal (CA-IS3730H, VIN = 0 V) | IDDB | 2.1 | 3.8 | mA | ENB = VDDB; VIN = 0V (CA-IS3730H) | 10 | |
| Supply current IDDA, AC 100Mbps (50MHz) | IDDA | 2.2 | 4.5 | mA | ENB = VDDB; all channel inputs 50% duty square wave, 5 V; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Supply current IDDB, AC 100Mbps (50MHz) | IDDB | 18.1 | 42 | mA | ENB = VDDB; all channel inputs 50% duty square wave, 5 V; CL = 15 pF; 100Mbps (50MHz) | 10 | |
| Output voltage logic high | VOH | 4.8 | V | IOH = -4mA; 图 8-2 | 9 | ||
| Thermal resistance, junction to ambient (SOIC16-WB) | RθJA | 83.4 | °C/W | SOIC16-WB (W) package column | 6 | ||
| Output impedance | ZO | 50 | Ω | 9 | |||
| Input capacitance | CI | 2 | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 9 |
CAD (KiCad official)
- Symbol:
CA-IS3730HW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is3730hw-etched.step/ca-is3730hw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3730hw.step/ca-is3730hw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
3334f70aba2bcfaf, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).