component

CA-IS3722CLS

Public Made by Adom

by adom

Chipanalog Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsignal isolation devicesca-is3722clsfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers ca-is3722cls: viewers · Ray 8d ago
ca-is3722cls-etched.glb Publish 0.1.0 · Ray 8d ago
ca-is3722cls-etched.step ca-is3722cls: factory component page (tier=lcsc) · Ray 8d ago
ca-is3722cls-hero.glb ca-is3722cls: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
ca-is3722cls-hero.overlay.json Publish 0.1.0 · Ray 8d ago
ca-is3722cls.glb Publish 0.1.0 · Ray 8d ago
ca-is3722cls.kicad_mod Publish 0.1.0 · Ray 8d ago
ca-is3722cls.kicad_sym Publish 0.1.0 · Ray 8d ago
ca-is3722cls.lbr Publish 0.1.0 · Ray 8d ago
ca-is3722cls.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

CA-IS3722CLS

Chipanalog · Digital Isolators · SOIC-8

CA-IS3722CLS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side-A supply voltage, recommended operating range 3.0 V to 5.5 V, absolute maximum 7.0 V referenced to GNDA; place 0.1 µF and 1 µF bypass capacitors close to this pin.
2 VO1 output Side-A channel 1 logic output on the CA-IS3722C, rail-to-rail with about 50 Ω output impedance, rated ±4 mA at VDDO = 5 V and ±2 mA at VDDO = 3.3 V.
3 VI2 input Side-A channel 2 logic input on the CA-IS3722C, Schmitt-trigger input with thresholds of 0.7 × VDDA (high) and 0.3 × VDDA (low).
4 GNDA power_in Side-A ground reference point, to which all side-A voltages are referenced.
5 GNDB power_in Side-B ground reference point, to which all side-B voltages are referenced.
6 VO2 output Side-B channel 2 logic output on the CA-IS3722C, rail-to-rail with about 50 Ω output impedance, rated ±4 mA at VDDO = 5 V and ±2 mA at VDDO = 3.3 V.
7 VI1 input Side-B channel 1 logic input on the CA-IS3722C, Schmitt-trigger input with thresholds of 0.7 × VDDB (high) and 0.3 × VDDB (low).
8 VDDB power_in Side-B supply voltage, recommended operating range 3.0 V to 5.5 V, absolute maximum 7.0 V referenced to GNDB; place 0.1 µF and 1 µF bypass capacitors close to this pin.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB (absolute max) VDDA, VDDB -0.5 7 V 6
Input voltage VIx (absolute max, printed as VDDI + 0.5 with footnote 3) VIN -0.5 V 6
Output current IO (absolute max) IO -20 20 mA 6
Junction temperature TJ (absolute max) TJ 150 °C 6
Storage temperature range TSTG (absolute max) TSTG -65 150 °C 6
ESD human body model VESD -8000 8000 V HBM per ANSI/ESDA/JEDEC JS-001, same-side pins 6
ESD charged device model VESD -2000 2000 V CDM per JEDEC JESD22-C101, all pins 6
Supply voltage VDDA, VDDB (recommended) VDDA, VDDB 3 3.3 5.5 V 6
VDD undervoltage threshold rising (UVLO+) VDD(UVLO+) 2.55 2.7 2.85 V VDD rising 6
VDD undervoltage threshold falling (UVLO-) VDD(UVLO-) 2.35 2.5 2.65 V VDD falling 6
UVLO hysteresis VHYS(UVLO) 150 200 270 mV 6
High-level output current IOH IOH -4 mA VDDO1 = 5V 6
High-level output current IOH IOH -2 mA VDDO1 = 3.3V 6
Low-level output current IOL IOL 4 mA VDDO1 = 5V 6
Low-level output current IOL IOL 2 mA VDDO1 = 3.3V 6
Input threshold logic low VIL (printed max 0.3 × VDDI2) VIL 0 V 6
Signal data rate DR DR 0 40 Mbps 6
Ambient temperature TA TA -40 27 125 °C 6
Output logic low voltage VOL (5V) VOL 0.2 0.4 V VDDA = VDDB = 5V ±10%, TA = -40 to 125°C; IOL = 4mA; Fig 8-1 10
Input high leakage current IIH (5V) IIH 20 µA VDDA = VDDB = 5V ±10%; VIH = VDDI1 at VIx 10
Input low leakage current IIL (5V) IIL -20 µA VDDA = VDDB = 5V ±10%; VIL = 0V at VIx 10
Common-mode transient immunity CMTI (5V) CMTI 100 150 kV/µs VDDA = VDDB = 5V ±10%; VI = VDDI1 or 0V, VCM = 1200V; Fig 8-3 10
Output logic low voltage VOL (3.3V) VOL 0.2 0.4 V VDDA = VDDB = 3.3V ±10%, TA = -40 to 125°C; IOL = 2mA; Fig 8-1 10
Input high leakage current IIH (3.3V) IIH 20 µA VDDA = VDDB = 3.3V ±10%; VIH = VDDI1 at VIx 10
Input low leakage current IIL (3.3V) IIL -20 µA VDDA = VDDB = 3.3V ±10%; VIL = 0V at VIx 10
Common-mode transient immunity CMTI (3.3V) CMTI 100 150 kV/µs VDDA = VDDB = 3.3V ±10%; VI = VDDI1 or 0V, VCM = 1200V; Fig 8-3 10
Supply current IDDA, DC, VIN = 0V (CL) IDDA 1.8 3.4 mA VDDA = VDDB = 5V ±10%; DC signal; VIN = 0V (CA-IS3722CL) 11
Supply current IDDB, DC, VIN = 0V (CL) IDDB 1.9 3.5 mA VDDA = VDDB = 5V ±10%; DC signal; VIN = 0V (CA-IS3722CL) 11
Supply current IDDA, DC, VIN = VDDI1 (CL) IDDA 3.3 4.9 mA VDDA = VDDB = 5V ±10%; DC signal; VIN = VDDI1 (CA-IS3722CL) 11
Supply current IDDB, DC, VIN = VDDI1 (CL) IDDB 3.4 5 mA VDDA = VDDB = 5V ±10%; DC signal; VIN = VDDI1 (CA-IS3722CL) 11
Supply current IDDA, AC 1Mbps (500kHz) IDDA 2.6 5.4 mA VDDA = VDDB = 5V ±10%; all inputs 50% duty square wave, 5V amplitude; CL = 15pF; 1Mbps (500kHz) 11
Supply current IDDB, AC 1Mbps (500kHz) IDDB 2.7 5.5 mA VDDA = VDDB = 5V ±10%; all inputs 50% duty square wave, 5V amplitude; CL = 15pF; 1Mbps (500kHz) 11
Supply current IDDA, AC 10Mbps (5MHz) IDDA 3.3 6.5 mA VDDA = VDDB = 5V ±10%; all inputs 50% duty square wave, 5V amplitude; CL = 15pF; 10Mbps (5MHz) 11
Supply current IDDB, AC 10Mbps (5MHz) IDDB 3.4 6.6 mA VDDA = VDDB = 5V ±10%; all inputs 50% duty square wave, 5V amplitude; CL = 15pF; 10Mbps (5MHz) 11
Supply current IDDA, AC 40Mbps (20MHz) IDDA 5.3 9.5 mA VDDA = VDDB = 5V ±10%; all inputs 50% duty square wave, 5V amplitude; CL = 15pF; 40Mbps (20MHz) 11
Supply current IDDB, AC 40Mbps (20MHz) IDDB 5.4 9.6 mA VDDA = VDDB = 5V ±10%; all inputs 50% duty square wave, 5V amplitude; CL = 15pF; 40Mbps (20MHz) 11
Supply current IDDA, DC, VIN = 0V (CL), 3.3V IDDA 1.8 3.2 mA VDDA = VDDB = 3.3V ±10%; DC signal; VIN = 0V (CA-IS3722CL) 12
Supply current IDDB, DC, VIN = 0V (CL), 3.3V IDDB 1.8 3.2 mA VDDA = VDDB = 3.3V ±10%; DC signal; VIN = 0V (CA-IS3722CL) 12
Supply current IDDA, DC, VIN = VDDI1 (CL), 3.3V IDDA 3.1 4.9 mA VDDA = VDDB = 3.3V ±10%; DC signal; VIN = VDDI1 (CA-IS3722CL) 12
Supply current IDDB, DC, VIN = VDDI1 (CL), 3.3V IDDB 3.2 5 mA VDDA = VDDB = 3.3V ±10%; DC signal; VIN = VDDI1 (CA-IS3722CL) 12
Supply current IDDA, AC 1Mbps (500kHz), 3.3V IDDA 2.5 5.4 mA VDDA = VDDB = 3.3V ±10%; all inputs 50% duty square wave, 3.3V amplitude; CL = 15pF; 1Mbps (500kHz) 12
Supply current IDDB, AC 1Mbps (500kHz), 3.3V IDDB 2.6 5.4 mA VDDA = VDDB = 3.3V ±10%; all inputs 50% duty square wave, 3.3V amplitude; CL = 15pF; 1Mbps (500kHz) 12
Supply current IDDA, AC 10Mbps (5MHz), 3.3V IDDA 3 6 mA VDDA = VDDB = 3.3V ±10%; all inputs 50% duty square wave, 3.3V amplitude; CL = 15pF; 10Mbps (5MHz) 12
Supply current IDDB, AC 10Mbps (5MHz), 3.3V IDDB 3.1 6.1 mA VDDA = VDDB = 3.3V ±10%; all inputs 50% duty square wave, 3.3V amplitude; CL = 15pF; 10Mbps (5MHz) 12
Supply current IDDA, AC 40Mbps (20MHz), 3.3V IDDA 4.3 8 mA VDDA = VDDB = 3.3V ±10%; all inputs 50% duty square wave, 3.3V amplitude; CL = 15pF; 40Mbps (20MHz) 12
Supply current IDDB, AC 40Mbps (20MHz), 3.3V IDDB 4.4 8.1 mA VDDA = VDDB = 3.3V ±10%; all inputs 50% duty square wave, 3.3V amplitude; CL = 15pF; 40Mbps (20MHz) 12
Minimum pulse width PWmin (5V) PWmin 20 ns VDDA = VDDB = 5V ±10% 13
Propagation delay tPLH, tPHL (5V) tPLH, tPHL 22 35 ns VDDA = VDDB = 5V ±10%; Fig 8-1 13
Pulse width distortion /tPLH - tPHL/ (5V) PWD 2.5 10 ns VDDA = VDDB = 5V ±10% 13
Channel-to-channel output skew tsk(o) (5V) tsk(o) 1 3 ns VDDA = VDDB = 5V ±10%; same-direction channels 13
Part-to-part channel output skew tsk(pp) (5V) tsk(pp) 1 7 ns VDDA = VDDB = 5V ±10% 13
Output rise time tr (5V) tr 2.5 4.8 ns VDDA = VDDB = 5V ±10%; Fig 8-1 13
Output fall time tf (5V) tf 2.5 4.8 ns VDDA = VDDB = 5V ±10%; Fig 8-1 13
Default output delay from input supply power-down tDO (5V) tDO 10 15 ns VDDA = VDDB = 5V ±10%; Fig 8-2 13
Startup time tSU (5V) tSU 25 37 µs VDDA = VDDB = 5V ±10% 13
Output impedance ZO (5V) ZO 50 Ω VDDA = VDDB = 5V ±10%; normal isolator channel, note 2: approx. ±40% 10
Output impedance ZO (3.3V) ZO 50 Ω VDDA = VDDB = 3.3V ±10%; normal isolator channel, note 2: approx. ±40% 10
Input capacitance CI (5V) CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1MHz, VDD = 5V 10
Input capacitance CI (3.3V) CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1MHz, VDD = 3.3V 10
Thermal resistance junction-to-ambient RθJA, SOIC8-NB (S) RθJA 109 °C/W SOIC8-NB (S) package 7

CAD (KiCad official)

  • Symbol: CA-IS3722CLS
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ca-is3722cls-etched.step / ca-is3722cls-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3722cls.step / ca-is3722cls.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (24 pp, sha256 914df7c2f5fc039d, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF