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CA-IS3721LW

Public Made by Adom

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Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3721LW

Chipanalog · Digital Isolators · SOIC-16-300mil

CA-IS3721LW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GNDA power_in A-side ground reference for the A-side supply and logic pins.
2 NC unconnected No internal connection; may be left floating, tied to VDD, or tied to GND.
3 VDDA power_in A-side supply voltage, recommended 2.375 V to 5.5 V (absolute maximum 6.0 V), with a 0.1 µF to 1 µF bypass capacitor required.
4 VI1 input A-side logic input of the forward channel; Schmitt-trigger input with VIH minimum 2.0 V and VIL maximum 0.8 V.
5 VO2 output A-side logic output of the reverse channel, with typical 50 Ω output impedance and recommended IOH/IOL up to 4 mA at a 5 V supply.
6 NC unconnected No internal connection; may be left floating, tied to VDD, or tied to GND.
7 GNDA power_in A-side ground reference for the A-side supply and logic pins.
8 NC unconnected No internal connection; may be left floating, tied to VDD, or tied to GND.
9 GNDB power_in B-side ground reference for the B-side supply and logic pins, isolated from GNDA.
10 NC unconnected No internal connection; may be left floating, tied to VDD, or tied to GND.
11 NC unconnected No internal connection; may be left floating, tied to VDD, or tied to GND.
12 VI2 input B-side logic input of the reverse channel; Schmitt-trigger input with positive threshold 1.4 V to 1.9 V and negative threshold 1.0 V to 1.4 V at 5 V.
13 VO1 output B-side logic output of the forward channel; on loss of input-side power the L-suffix device drives this output low (default-low fail-safe), with default output delay typically 8 ns to 12 ns.
14 VDDB power_in B-side supply voltage, recommended 2.375 V to 5.5 V (absolute maximum 6.0 V), with a 0.1 µF to 1 µF bypass capacitor required.
15 NC unconnected No internal connection; may be left floating, tied to VDD, or tied to GND.
16 GNDB power_in B-side ground reference for the B-side supply and logic pins, isolated from GNDA.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage, VDDA/VDDB (peak, relative to local GND) VDDA, VDDB -0.5 6 V Relative to local GND (GNDA or GNDB), peak values 6
Input voltage (Ax, Bx, ENx) Vin -0.5 V Ax, Bx, ENx; printed max VDDA+0.5 6
Output current IO -20 20 mA 6
Junction temperature TJ 150 °C 6
Storage temperature range TSTG -65 150 °C 6
Supply voltage, VDDA/VDDB VDDA, VDDB 2.375 3.3 5.5 V 6
VDD undervoltage threshold, rising (UVLO+) VDD(UVLO+) 1.95 2.24 2.375 V VDD rising 6
VDD undervoltage threshold, falling (UVLO-) VDD(UVLO-) 1.88 2.1 2.325 V VDD falling 6
VDD undervoltage hysteresis VHYS(UVLO) 70 140 250 mV 6
High-level output current, VDDO = 5 V IOH -4 mA VDDO = 5V 6
High-level output current, VDDO = 3.3 V IOH -2 mA VDDO = 3.3V 6
High-level output current, VDDO = 2.5 V IOH -1 mA VDDO = 2.5V 6
Low-level output current, VDDO = 5 V IOL 4 mA VDDO = 5V 6
Low-level output current, VDDO = 3.3 V IOL 2 mA VDDO = 3.3V 6
Low-level output current, VDDO = 2.5 V IOL 1 mA VDDO = 2.5V 6
Input threshold logic high VIH 2 V 6
Input threshold logic low VIL 0.8 V 6
Signal data rate DR 0 150 Mbps 6
Ambient temperature TA -40 27 125 °C 6
Output voltage logic low VOL 0.2 0.4 V IOL = 4mA; Fig 8-1 10
Positive input threshold VIT+(IN) 1.4 1.67 1.9 V 10
Negative input threshold VIT-(IN) 1 1.23 1.4 V 10
Input threshold hysteresis VI(HYS) 0.3 0.44 0.5 V 10
Input high-level leakage current IIH 4 µA VIH = VDDA at Ax or Bx or ENx 10
Input low-level leakage current IIL -4 µA VIL = 0 V at Ax or Bx 10
Common-mode transient immunity CMTI 75 100 kV/µS VI = VDDI1 or 0 V, VCM = 1200 V; Fig 8-3 10
Output impedance tolerance (about 50 Ω ±40%) ZO -40 40 % Normal isolator channel output impedance about 50 Ω ±40% (note 2) 10
Supply current IDDA, DC signal IDDA 1.3 2 mA VIN = 0V (CA-IS3721L) 11
Supply current IDDB, DC signal IDDB 1.3 2 mA VIN = 0V (CA-IS3721L) 11
Supply current IDDA, DC signal IDDA 2.1 3.1 mA VIN = VDDI (CA-IS3721L) 11
Supply current IDDB, DC signal IDDB 2.1 3.1 mA VIN = VDDI (CA-IS3721L) 11
Supply current IDDA, AC signal 1 Mbps IDDA 1.8 2.6 mA All inputs 50% duty 5V square wave; CL = 15 pF; 1Mbps (500kHz) 11
Supply current IDDB, AC signal 1 Mbps IDDB 1.8 2.6 mA All inputs 50% duty 5V square wave; CL = 15 pF; 1Mbps (500kHz) 11
Supply current IDDA, AC signal 10 Mbps IDDA 2.2 3.3 mA All inputs 50% duty 5V square wave; CL = 15 pF; 10Mbps (5MHz) 11
Supply current IDDB, AC signal 10 Mbps IDDB 2.2 3.3 mA All inputs 50% duty 5V square wave; CL = 15 pF; 10Mbps (5MHz) 11
Supply current IDDA, AC signal 100 Mbps IDDA 7 10.5 mA All inputs 50% duty 5V square wave; CL = 15 pF; 100Mbps (50MHz) 11
Supply current IDDB, AC signal 100 Mbps IDDB 7 10.5 mA All inputs 50% duty 5V square wave; CL = 15 pF; 100Mbps (50MHz) 11
Data rate DR 0 150 Mbps 14
Minimum pulse width PWmin 5 ns 14
Propagation delay tPLH, tPHL 5 8 13 ns Fig 8-1 14
Pulse width distortion PWD 0.2 4.5 ns /tPLH - tPHL/ 14
Channel-to-channel output skew tsk(o) 0.4 2.5 ns Same-direction channels (1 同方向通道) 14
Part-to-part skew tsk(pp) 2 4.5 ns Same supply voltage, temperature, input signal and load 14
Output rise time tr 2.5 4 ns Fig 8-1 14
Output fall time tf 2.5 4 ns Fig 8-1 14
Default output delay time from input power loss tDO 8 12 ns Fig 8-2 14
Startup time tSU 15 40 µs 14
Output voltage logic high VOH 4.8 V IOH = -4mA; Fig 8-1 10
Normal channel output impedance ZO 50 Ω 10
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V 10
Junction-to-ambient thermal resistance RθJA 86.5 °C/W 16-pin SOIC (W) package 7
Junction-to-case (top) thermal resistance RθJC(top) 49.6 °C/W 16-pin SOIC (W) package 7
Junction-to-board thermal resistance RθJB 49.7 °C/W 16-pin SOIC (W) package 7
Junction-to-top characterization parameter ψJT 32.3 °C/W 16-pin SOIC (W) package 7
Junction-to-board characterization parameter ψJB 49.2 °C/W 16-pin SOIC (W) package 7

CAD (KiCad official)

  • Symbol: CA-IS3721LW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3721lw-etched.step / ca-is3721lw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3721lw.step / ca-is3721lw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (25 pp, sha256 e0570f476c6a89dd, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF