component
CA-IS3721LS
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CA-IS3721LS
Chipanalog · Digital Isolators · SOIC-8
CA-IS3721LS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A supply voltage, 2.375 V to 5.5 V recommended operating range, bypassed with a 0.1 µF to 1 µF capacitor. |
| 2 | VI1 | input | Side A logic input for channel 1 (forward channel, transmitted to VO1 on side B) with Schmitt-trigger input. |
| 3 | VO2 | output | Side A logic output for channel 2 (reverse channel, driven from VI2 on side B). |
| 4 | GNDA | power_in | Side A ground reference. |
| 5 | GNDB | power_in | Side B ground reference. |
| 6 | VI2 | input | Side B logic input for channel 2 (reverse channel, transmitted to VO2 on side A) with Schmitt-trigger input. |
| 7 | VO1 | output | Side B logic output for channel 1 (forward channel, follows VI1 on side A). |
| 8 | VDDB | power_in | Side B supply voltage, 2.375 V to 5.5 V recommended operating range, bypassed with a 0.1 µF to 1 µF capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute max) | VDDA, VDDB | -0.5 | 6 | V | 6 | ||
| Input voltage | Vin | -0.5 | V | Ax, Bx, ENx; max VDDA+0.5, not to exceed 6 V | 6 | ||
| Output current | IO | -20 | 20 | mA | 6 | ||
| Junction temperature | TJ | 150 | °C | 6 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 6 | ||
| ESD HBM | VESD | -4000 | 4000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 6 | |
| ESD CDM | VESD | -1000 | 1000 | V | JESD22-C101, all pins | 6 | |
| Supply voltage | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | 6 | |
| UVLO rising threshold | VDD(UVLO+) | 1.95 | 2.24 | 2.375 | V | VDD rising | 6 |
| UVLO falling threshold | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | VDD falling | 6 |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 6 | |
| High-level output current | IOH | -4 | mA | VDDO = 5V (-2 at 3.3V, -1 at 2.5V) | 6 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5V (2 at 3.3V, 1 at 2.5V) | 6 | ||
| Input threshold logic high | VIH | 2 | V | 6 | |||
| Input threshold logic low | VIL | 0.8 | V | 6 | |||
| Signal rate | DR | 0 | 150 | Mbps | 6 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 137.7 | °C/W | S (SOIC 8 pin) | 7 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 54.9 | °C/W | S (SOIC 8 pin) | 7 | ||
| Junction-to-board thermal resistance | RθJB | 71.7 | °C/W | S (SOIC 8 pin) | 7 | ||
| Maximum power dissipation | PD | 120 | mW | CA-IS3721; VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave | 7 | ||
| Maximum power dissipation side A | PDA | 60 | mW | CA-IS3721 | 7 | ||
| Maximum power dissipation side B | PDB | 60 | mW | CA-IS3721 | 7 | ||
| High-level output voltage | VOH | 4.8 | V | IOH = -4mA; VDD = 5V ±10%; min is VDDO-0.4 | 10 | ||
| Low-level output voltage | VOL | 0.2 | 0.4 | V | IOL = 4mA; VDD = 5V ±10% | 10 | |
| Positive input threshold | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | VDD = 5V ±10% | 10 |
| Negative input threshold | VIT-(IN) | 1 | 1.23 | 1.4 | V | VDD = 5V ±10% | 10 |
| Input threshold hysteresis | VI(HYS) | 0.3 | 0.44 | 0.5 | V | VDD = 5V ±10% | 10 |
| Input high leakage current | IIH | 4 | µA | VIH = VDDA at Ax or Bx or ENx | 10 | ||
| Input low leakage current | IIL | -4 | µA | VIL = 0 V at Ax or Bx | 10 | ||
| Output impedance | ZO | 50 | Ω | 10 | |||
| Common-mode transient immunity | CMTI | 75 | 100 | kV/µs | VI = VDDI or 0 V, VCM = 1200 V; Figure 8-3 | 10 | |
| Input capacitance | CI | 2 | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 10 | ||
| Data rate | DR | 0 | 150 | Mbps | VDD = 5V ±10% | 14 | |
| Minimum pulse width | PWmin | 5 | ns | VDD = 5V ±10% | 14 | ||
| Propagation delay | tPLH, tPHL | 5 | 8 | 13 | ns | Figure 8-1; VDD = 5V ±10% | 14 |
| Pulse width distortion | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/; VDD = 5V ±10% | 14 | |
| Channel-to-channel output skew | tsk(o) | 0.4 | 2.5 | ns | same-direction channels; VDD = 5V ±10% | 14 | |
| Part-to-part skew time | tsk(pp) | 2 | 4.5 | ns | VDD = 5V ±10% | 14 | |
| Output rise time | tr | 2.5 | 4 | ns | Figure 8-1; VDD = 5V ±10% | 14 | |
| Output fall time | tf | 2.5 | 4 | ns | Figure 8-1; VDD = 5V ±10% | 14 | |
| Default output delay time from input power loss | tDO | 8 | 12 | ns | Figure 8-2; VDD = 5V ±10% | 14 | |
| Start-up time | tSU | 15 | 40 | µs | VDD = 5V ±10% | 14 | |
| Supply current IDDA, DC signal (VIN=0V for L) | IDDA | 1.3 | 2 | mA | CA-IS3721L, VIN = 0V; VDD = 5V ±10% | 11 | |
| Supply current IDDB, DC signal (VIN=0V for L) | IDDB | 1.3 | 2 | mA | CA-IS3721L, VIN = 0V; VDD = 5V ±10% | 11 | |
| Supply current IDDA, DC signal (VIN=VDDI for L) | IDDA | 2.1 | 3.1 | mA | CA-IS3721L, VIN = VDDI; VDD = 5V ±10% | 11 | |
| Supply current IDDB, DC signal (VIN=VDDI for L) | IDDB | 2.1 | 3.1 | mA | CA-IS3721L, VIN = VDDI; VDD = 5V ±10% | 11 | |
| Supply current IDDA at 1Mbps | IDDA | 1.8 | 2.6 | mA | 1Mbps (500kHz), CL = 15 pF; VDD = 5V ±10% | 11 | |
| Supply current IDDB at 1Mbps | IDDB | 1.8 | 2.6 | mA | 1Mbps (500kHz), CL = 15 pF; VDD = 5V ±10% | 11 | |
| Supply current IDDA at 10Mbps | IDDA | 2.2 | 3.3 | mA | 10Mbps (5MHz), CL = 15 pF; VDD = 5V ±10% | 11 | |
| Supply current IDDB at 10Mbps | IDDB | 2.2 | 3.3 | mA | 10Mbps (5MHz), CL = 15 pF; VDD = 5V ±10% | 11 | |
| Supply current IDDA at 100Mbps | IDDA | 7 | 10.5 | mA | 100Mbps (50MHz), CL = 15 pF; VDD = 5V ±10% | 11 | |
| Supply current IDDB at 100Mbps | IDDB | 7 | 10.5 | mA | 100Mbps (50MHz), CL = 15 pF; VDD = 5V ±10% | 11 | |
| Maximum isolation voltage | VISO | 3750 | VRMS | UL 1577, VTEST = VISO, t = 60 s; S package | 8 |
CAD (KiCad official)
- Symbol:
CA-IS3721LS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ca-is3721ls-etched.step/ca-is3721ls-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3721ls.step/ca-is3721ls.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
3f67653faec8df59, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CA-IS3721LS
**Chipanalog** · Digital Isolators · SOIC-8
CA-IS3721LS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A supply voltage, 2.375 V to 5.5 V recommended operating range, bypassed with a 0.1 µF to 1 µF capacitor. |
| 2 | VI1 | input | Side A logic input for channel 1 (forward channel, transmitted to VO1 on side B) with Schmitt-trigger input. |
| 3 | VO2 | output | Side A logic output for channel 2 (reverse channel, driven from VI2 on side B). |
| 4 | GNDA | power_in | Side A ground reference. |
| 5 | GNDB | power_in | Side B ground reference. |
| 6 | VI2 | input | Side B logic input for channel 2 (reverse channel, transmitted to VO2 on side A) with Schmitt-trigger input. |
| 7 | VO1 | output | Side B logic output for channel 1 (forward channel, follows VI1 on side A). |
| 8 | VDDB | power_in | Side B supply voltage, 2.375 V to 5.5 V recommended operating range, bypassed with a 0.1 µF to 1 µF capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute max) | VDDA, VDDB | -0.5 | | 6 | V | | 6 |
| Input voltage | Vin | -0.5 | | | V | Ax, Bx, ENx; max VDDA+0.5, not to exceed 6 V | 6 |
| Output current | IO | -20 | | 20 | mA | | 6 |
| Junction temperature | TJ | | | 150 | °C | | 6 |
| Storage temperature range | TSTG | -65 | | 150 | °C | | 6 |
| ESD HBM | VESD | -4000 | | 4000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 6 |
| ESD CDM | VESD | -1000 | | 1000 | V | JESD22-C101, all pins | 6 |
| Supply voltage | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | | 6 |
| UVLO rising threshold | VDD(UVLO+) | 1.95 | 2.24 | 2.375 | V | VDD rising | 6 |
| UVLO falling threshold | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | VDD falling | 6 |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | | 6 |
| High-level output current | IOH | -4 | | | mA | VDDO = 5V (-2 at 3.3V, -1 at 2.5V) | 6 |
| Low-level output current | IOL | | | 4 | mA | VDDO = 5V (2 at 3.3V, 1 at 2.5V) | 6 |
| Input threshold logic high | VIH | 2 | | | V | | 6 |
| Input threshold logic low | VIL | | | 0.8 | V | | 6 |
| Signal rate | DR | 0 | | 150 | Mbps | | 6 |
| Ambient temperature | TA | -40 | 27 | 125 | °C | | 6 |
| Junction-to-ambient thermal resistance | RθJA | | 137.7 | | °C/W | S (SOIC 8 pin) | 7 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 54.9 | | °C/W | S (SOIC 8 pin) | 7 |
| Junction-to-board thermal resistance | RθJB | | 71.7 | | °C/W | S (SOIC 8 pin) | 7 |
| Maximum power dissipation | PD | | | 120 | mW | CA-IS3721; VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75MHz 50% duty square wave | 7 |
| Maximum power dissipation side A | PDA | | | 60 | mW | CA-IS3721 | 7 |
| Maximum power dissipation side B | PDB | | | 60 | mW | CA-IS3721 | 7 |
| High-level output voltage | VOH | | 4.8 | | V | IOH = -4mA; VDD = 5V ±10%; min is VDDO-0.4 | 10 |
| Low-level output voltage | VOL | | 0.2 | 0.4 | V | IOL = 4mA; VDD = 5V ±10% | 10 |
| Positive input threshold | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | VDD = 5V ±10% | 10 |
| Negative input threshold | VIT-(IN) | 1 | 1.23 | 1.4 | V | VDD = 5V ±10% | 10 |
| Input threshold hysteresis | VI(HYS) | 0.3 | 0.44 | 0.5 | V | VDD = 5V ±10% | 10 |
| Input high leakage current | IIH | | | 4 | µA | VIH = VDDA at Ax or Bx or ENx | 10 |
| Input low leakage current | IIL | -4 | | | µA | VIL = 0 V at Ax or Bx | 10 |
| Output impedance | ZO | | 50 | | Ω | | 10 |
| Common-mode transient immunity | CMTI | 75 | 100 | | kV/µs | VI = VDDI or 0 V, VCM = 1200 V; Figure 8-3 | 10 |
| Input capacitance | CI | | 2 | | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 10 |
| Data rate | DR | 0 | | 150 | Mbps | VDD = 5V ±10% | 14 |
| Minimum pulse width | PWmin | | | 5 | ns | VDD = 5V ±10% | 14 |
| Propagation delay | tPLH, tPHL | 5 | 8 | 13 | ns | Figure 8-1; VDD = 5V ±10% | 14 |
| Pulse width distortion | PWD | | 0.2 | 4.5 | ns | /tPLH - tPHL/; VDD = 5V ±10% | 14 |
| Channel-to-channel output skew | tsk(o) | | 0.4 | 2.5 | ns | same-direction channels; VDD = 5V ±10% | 14 |
| Part-to-part skew time | tsk(pp) | | 2 | 4.5 | ns | VDD = 5V ±10% | 14 |
| Output rise time | tr | | 2.5 | 4 | ns | Figure 8-1; VDD = 5V ±10% | 14 |
| Output fall time | tf | | 2.5 | 4 | ns | Figure 8-1; VDD = 5V ±10% | 14 |
| Default output delay time from input power loss | tDO | | 8 | 12 | ns | Figure 8-2; VDD = 5V ±10% | 14 |
| Start-up time | tSU | | 15 | 40 | µs | VDD = 5V ±10% | 14 |
| Supply current IDDA, DC signal (VIN=0V for L) | IDDA | | 1.3 | 2 | mA | CA-IS3721L, VIN = 0V; VDD = 5V ±10% | 11 |
| Supply current IDDB, DC signal (VIN=0V for L) | IDDB | | 1.3 | 2 | mA | CA-IS3721L, VIN = 0V; VDD = 5V ±10% | 11 |
| Supply current IDDA, DC signal (VIN=VDDI for L) | IDDA | | 2.1 | 3.1 | mA | CA-IS3721L, VIN = VDDI; VDD = 5V ±10% | 11 |
| Supply current IDDB, DC signal (VIN=VDDI for L) | IDDB | | 2.1 | 3.1 | mA | CA-IS3721L, VIN = VDDI; VDD = 5V ±10% | 11 |
| Supply current IDDA at 1Mbps | IDDA | | 1.8 | 2.6 | mA | 1Mbps (500kHz), CL = 15 pF; VDD = 5V ±10% | 11 |
| Supply current IDDB at 1Mbps | IDDB | | 1.8 | 2.6 | mA | 1Mbps (500kHz), CL = 15 pF; VDD = 5V ±10% | 11 |
| Supply current IDDA at 10Mbps | IDDA | | 2.2 | 3.3 | mA | 10Mbps (5MHz), CL = 15 pF; VDD = 5V ±10% | 11 |
| Supply current IDDB at 10Mbps | IDDB | | 2.2 | 3.3 | mA | 10Mbps (5MHz), CL = 15 pF; VDD = 5V ±10% | 11 |
| Supply current IDDA at 100Mbps | IDDA | | 7 | 10.5 | mA | 100Mbps (50MHz), CL = 15 pF; VDD = 5V ±10% | 11 |
| Supply current IDDB at 100Mbps | IDDB | | 7 | 10.5 | mA | 100Mbps (50MHz), CL = 15 pF; VDD = 5V ±10% | 11 |
| Maximum isolation voltage | VISO | 3750 | | | VRMS | UL 1577, VTEST = VISO, t = 60 s; S package | 8 |
## CAD (KiCad official)
- Symbol: `CA-IS3721LS`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ca-is3721ls-etched.step` / `ca-is3721ls-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is3721ls.step` / `ca-is3721ls.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Chipanalog datasheet](docs/ca-is3721ls-datasheet.pdf) (25 pp, sha256 `3f67653faec8df59`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ca-is3721ls-datasheet.pdf)