component

CA-IS3721LG

Public Made by Adom

by adom

Chipanalog Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ca-is3721lgfactory-2.0.0extractor-text

Verified CA-IS3721LG

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CA-IS3721LG · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 25-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-6xpbhupd/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ca-is3721lg.kicad_sym✓ ca-is3721lg.kicad_mod✓ ca-is3721lg.step
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CA-IS3721LG

Chipanalog · Digital Isolators · SOIC-8

CA-IS3721LG from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in Side A supply voltage; the recommended operating range is 2.375 V to 5.5 V with 3.3 V typical.
2 VI1 input Side A logic input for channel 1 on the CA-IS3721; it is TTL-compatible with VIH minimum 2.0 V and VIL maximum 0.8 V.
3 VO2 output Side A logic output for channel 2 on the CA-IS3721 (reverse-direction channel); recommended IOH is -4 mA and IOL is 4 mA at 5 V (-2 mA / 2 mA at 3.3 V, -1 mA / 1 mA at 2.5 V).
4 GNDA power_in Side A ground reference point; all Side A signal and supply voltages are referenced to this pin.
5 GNDB power_in Side B ground reference point, isolated from GNDA by the isolation barrier; all Side B signal and supply voltages are referenced to this pin.
6 VI2 input Side B logic input for channel 2 on the CA-IS3721; it is TTL-compatible with VIH minimum 2.0 V and VIL maximum 0.8 V.
7 VO1 output Side B logic output for channel 1 on the CA-IS3721; recommended IOH is -4 mA and IOL is 4 mA at 5 V (-2 mA / 2 mA at 3.3 V, -1 mA / 1 mA at 2.5 V).
8 VDDB power_in Side B supply voltage; the recommended operating range is 2.375 V to 5.5 V with 3.3 V typical.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB (absolute maximum) VDDA, VDDB -0.5 7 V 6
Input voltage Ax, Bx (absolute maximum) Vin -0.5 V 6
Output current (absolute maximum) IO -20 20 mA 6
Junction temperature (absolute maximum) TJ 150 °C 6
Storage temperature range (absolute maximum) TSTG -65 150 °C 6
Supply voltage VDDA, VDDB (recommended) VDDA, VDDB 2.375 3.3 5.5 V 6
UVLO threshold, supply rising VDD（UVLO+） 1.95 2.24 2.375 V 6
UVLO threshold, supply falling VDD（UVLO-） 1.88 2.1 2.325 V 6
UVLO hysteresis VHYS（UVLO） 70 140 250 mV 6
High-level output current IOH -4 mA VDDO1 = 5V 6
High-level output current IOH -2 mA VDDO = 3.3V 6
High-level output current IOH -1 mA VDDO = 2.5V 6
Low-level output current IOL 4 mA VDDO = 5V 6
Low-level output current IOL 2 mA VDDO = 3.3V 6
Low-level output current IOL 1 mA VDDO = 2.5V 6
Input threshold logic high (recommended) VIH 2 V 6
Input threshold logic low (recommended) VIL 0.8 V 6
Signal data rate DR 0 150 Mbps 6
Ambient temperature TA -40 27 125 °C 6
Output voltage logic low, 5V VOL 0.2 0.4 V IOL = 4mA; 图 8-1 (VDDA = VDDB = 5 V ± 10%) 10
Output voltage logic low, 3.3V VOL 0.2 0.4 V IOL = 4mA; 图 8-1 (VDDA = VDDB = 3.3 V ± 10%) 10
Output voltage logic low, 2.5V VOL 0.2 0.4 V IOL = 4mA; 图 8-1 (VDDA = VDDB = 2.5 V ± 5%) 10
Input threshold logic high VIT+(IN) 2 V 10
Input threshold logic low VIT-(IN) 0.8 V 10
Input high-level leakage current IIH 20 µA VIH = VDDA at Ax or Bx 10
Input low-level leakage current IIL -20 µA VIL = 0 V at Ax or Bx 10
Common-mode transient immunity, 5V CMTI 100 150 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 (VDDA = VDDB = 5 V ± 10%) 10
Common-mode transient immunity, 3.3V CMTI 100 150 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 (VDDA = VDDB = 3.3 V ± 10%) 10
Common-mode transient immunity, 2.5V CMTI 100 150 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 (VDDA = VDDB = 2.5 V ± 5%) 10
Output impedance tolerance ZO -40 40 % Normal isolator channel output impedance ~50Ω±40% 10
Supply current DC, A side (VIN = 0V) IDDA 1.6 3.2 mA VIN = 0V (CA-IS3721L); 5 V 11
Supply current DC, B side (VIN = 0V) IDDB 1.6 3.2 mA VIN = 0V (CA-IS3721L); 5 V 11
Supply current DC, A side (VIN = VDDI) IDDA 2.9 5.8 mA VIN = VDDI (CA-IS3721L); 5 V 11
Supply current DC, B side (VIN = VDDI) IDDB 2.9 5.8 mA VIN = VDDI (CA-IS3721L); 5 V 11
Supply current AC 1Mbps, A side IDDA 2.1 3.2 mA 所有通道输入 50%占空比，幅值为 5V 的方波；每个通道 CL = 15 pF; 1Mbps (500kHz) 11
Supply current AC 1Mbps, B side IDDB 2.1 3.2 mA 所有通道输入 50%占空比，幅值为 5V 的方波；每个通道 CL = 15 pF; 1Mbps (500kHz) 11
Supply current AC 10Mbps, A side IDDA 5.6 7.8 mA 所有通道输入 50%占空比，幅值为 5V 的方波；每个通道 CL = 15 pF; 10Mbps (5MHz) 11
Supply current AC 10Mbps, B side IDDB 5.6 7.8 mA 所有通道输入 50%占空比，幅值为 5V 的方波；每个通道 CL = 15 pF; 10Mbps (5MHz) 11
Supply current AC 100Mbps, A side IDDA 12.9 22 mA 所有通道输入 50%占空比，幅值为 5V 的方波；每个通道 CL = 15 pF; 100Mbps (50MHz) 11
Supply current AC 100Mbps, B side IDDB 12.9 22 mA 所有通道输入 50%占空比，幅值为 5V 的方波；每个通道 CL = 15 pF; 100Mbps (50MHz) 11
Minimum pulse width, 5V PWmin 5 ns 14
Propagation delay, 5V tPLH, tPHL 5 12 15 ns 图 8-1 14
Pulse width distortion, 5V PWD 0.2 4.5 ns /tPLH - tPHL/ 14
Channel-to-channel output skew, same direction, 5V tsk(o) 0.4 2.5 ns 同方向通道 14
Part-to-part channel output skew, 5V tsk(pp) 2 4.5 ns 14
Output rise time, 5V tr 2.5 4 ns 图 8-1 14
Output fall time, 5V tf 2.5 4 ns 图 8-1 14
Default output delay from supply loss, 5V tDO 8 12 ns 图 8-2 14
Start-up time, 5V tSU 15 40 µs 14
Input capacitance CI 2 pF VI = VDD/ 2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V 10
Normal channel output impedance ZO 50 Ω 10
Junction-to-ambient thermal resistance RθJA 92.3 °C/W SOIC8-WB(G) 7

CAD (KiCad official)

  • Symbol: CA-IS3721LG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ca-is3721lg-etched.step / ca-is3721lg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3721lg.step / ca-is3721lg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (25 pp, sha256 700fbcc87277736d, retrieved 2026-11-05, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF