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CA-IS3721HW
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IS3721HW
Chipanalog · Digital Isolators · SOIC-16-300mil
CA-IS3721HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GNDA | power_in | A-side ground reference point for the isolator's input side; GNDA is tied internally to pin 7. |
| 2 | NC | unconnected | No internal connection; the pin may be left floating or connected to VDD or GND. |
| 3 | VDDA | power_in | A-side supply voltage; recommended operating range is 2.375 V to 5.5 V (typical 3.3 V), with 0.1 µF to 1 µF bypass capacitance required. |
| 4 | VI1 | input | A-side logic input for channel 1 of CA-IS3721, TTL-compatible with Schmitt-trigger input (VIH 2.0 V min, VIL 0.8 V max). |
| 5 | VO2 | output | A-side logic output for channel 2 of CA-IS3721 (reverse channel); it drives the output as the RX side and defaults high on loss of input power or signal for the H-suffix device. |
| 6 | NC | unconnected | No internal connection; the pin may be left floating or connected to VDD or GND. |
| 7 | GNDA | power_in | A-side ground reference point for the isolator's input side; GNDA is tied internally to pin 1. |
| 8 | NC | unconnected | No internal connection; the pin may be left floating or connected to VDD or GND. |
| 9 | GNDB | power_in | B-side ground reference point for the isolated output side; GNDB is tied internally to pin 16. |
| 10 | NC | unconnected | No internal connection; the pin may be left floating or connected to VDD or GND. |
| 11 | NC | unconnected | No internal connection; the pin may be left floating or connected to VDD or GND. |
| 12 | VI2 | input | B-side logic input for channel 2 of CA-IS3721, TTL-compatible with Schmitt-trigger input (VIH 2.0 V min, VIL 0.8 V max). |
| 13 | VO1 | output | B-side logic output for channel 1 of CA-IS3721; it follows the A-side input and defaults high on loss of input power or signal for the H-suffix device. |
| 14 | VDDB | power_in | B-side supply voltage; recommended operating range is 2.375 V to 5.5 V (typical 3.3 V), with 0.1 µF to 1 µF bypass capacitance required. |
| 15 | NC | unconnected | No internal connection; the pin may be left floating or connected to VDD or GND. |
| 16 | GNDB | power_in | B-side ground reference point for the isolated output side; GNDB is tied internally to pin 9. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VDDA, VDDB | -0.5 | 6 | V | 6 | ||
| Input voltage (absolute maximum) | Vin | -0.5 | V | Ax, Bx, ENx; max = VDDA+0.5 (footnote 3: not to exceed 6 V) | 6 | ||
| Output current (absolute maximum) | IO | -20 | 20 | mA | 6 | ||
| Junction temperature (absolute maximum) | TJ | 150 | °C | 6 | |||
| Storage temperature range | TSTG | -65 | 150 | °C | 6 | ||
| Supply voltage (recommended) | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | 6 | |
| UVLO threshold, supply rising | VDD(UVLO+) | 1.95 | 2.24 | 2.375 | V | 6 | |
| UVLO threshold, supply falling | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | 6 | |
| UVLO hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 6 | |
| High-level output current | IOH | -4 | mA | VDDO = 5V | 6 | ||
| High-level output current | IOH | -2 | mA | VDDO = 3.3V | 6 | ||
| High-level output current | IOH | -1 | mA | VDDO = 2.5V | 6 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5V | 6 | ||
| Low-level output current | IOL | 2 | mA | VDDO = 3.3V | 6 | ||
| Low-level output current | IOL | 1 | mA | VDDO = 2.5V | 6 | ||
| Input threshold logic high | VIH | 2 | V | 6 | |||
| Input threshold logic low | VIL | 0.8 | V | 6 | |||
| Signal data rate | DR | 0 | 150 | Mbps | 6 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 6 | |
| Positive input threshold | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | VDDA = VDDB = 5 V ± 10% | 10 |
| Negative input threshold | VIT-(IN) | 1 | 1.23 | 1.4 | V | VDDA = VDDB = 5 V ± 10% | 10 |
| Input threshold hysteresis | VI(HYS) | 0.3 | 0.44 | 0.5 | V | VDDA = VDDB = 5 V ± 10% | 10 |
| Logic low output voltage | VOL | 0.2 | 0.4 | V | IOL = 4mA; 图 8-1 | 10 | |
| Input high leakage current | IIH | 4 | µA | VIH = VDDA at Ax or Bx or ENx | 10 | ||
| Input low leakage current | IIL | -4 | µA | VIL = 0 V at Ax or Bx | 10 | ||
| Output impedance tolerance | ZO | -40 | 40 | % | Note 2: normal isolator channel, approx. 50Ω ±40% | 10 | |
| Common-mode transient immunity | CMTI | 75 | 100 | kV/µS | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 10 | |
| Minimum pulse width | PWmin | 5 | ns | 14 | |||
| Propagation delay | tPLH, tPHL | 5 | 8 | 13 | ns | 图 8-1 | 14 |
| Pulse width distortion | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 14 | |
| Channel-to-channel output skew | tsk(o) | 0.4 | 2.5 | ns | same-direction channels (note 1) | 14 | |
| Part-to-part skew | tsk(pp) | 2 | 4.5 | ns | 14 | ||
| Output rise time | tr | 2.5 | 4 | ns | 图 8-1 | 14 | |
| Output fall time | tf | 2.5 | 4 | ns | 图 8-1 | 14 | |
| Default output delay from input power loss | tDO | 8 | 12 | ns | 图 8-2 | 14 | |
| Start-up time | tSU | 15 | 40 | µs | 14 | ||
| Supply current side A, DC | IDDA | 1.3 | 2 | mA | DC signal; VIN = VDDI (CA-IS3721H) | 11 | |
| Supply current side B, DC | IDDB | 1.3 | 2 | mA | DC signal; VIN = VDDI (CA-IS3721H) | 11 | |
| Supply current side A, 1Mbps | IDDA | 1.8 | 2.6 | mA | All channel inputs 50% duty 5V square wave; CL = 15 pF; 1Mbps (500kHz) | 11 | |
| Supply current side B, 1Mbps | IDDB | 1.8 | 2.6 | mA | All channel inputs 50% duty 5V square wave; CL = 15 pF; 1Mbps (500kHz) | 11 | |
| Supply current side A, 10Mbps | IDDA | 2.2 | 3.3 | mA | All channel inputs 50% duty 5V square wave; CL = 15 pF; 10Mbps (5MHz) | 11 | |
| Supply current side B, 10Mbps | IDDB | 2.2 | 3.3 | mA | All channel inputs 50% duty 5V square wave; CL = 15 pF; 10Mbps (5MHz) | 11 | |
| Supply current side A, 100Mbps | IDDA | 7 | 10.5 | mA | All channel inputs 50% duty 5V square wave; CL = 15 pF; 100Mbps (50MHz) | 11 | |
| Supply current side B, 100Mbps | IDDB | 7 | 10.5 | mA | All channel inputs 50% duty 5V square wave; CL = 15 pF; 100Mbps (50MHz) | 11 | |
| Logic high output voltage | VOH | 4.8 | V | IOH = -4mA; 图 8-1 | 10 | ||
| Output impedance | ZO | 50 | Ω | 10 | |||
| Input capacitance | CI | 2 | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 10 | ||
| Junction-to-ambient thermal resistance (W, 16-pin) | RθJA | 86.5 | °C/W | 7 | |||
| Junction-to-case (top) thermal resistance (W, 16-pin) | RθJC(top) | 49.6 | °C/W | 7 | |||
| Junction-to-board thermal resistance (W, 16-pin) | RθJB | 49.7 | °C/W | 7 | |||
| Junction-to-top characterization parameter (W, 16-pin) | ψJT | 32.3 | °C/W | 7 | |||
| Junction-to-board characterization parameter (W, 16-pin) | ψJB | 49.2 | °C/W | 7 |
CAD (KiCad official)
- Symbol:
CA-IS3721HW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is3721hw-etched.step/ca-is3721hw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3721hw.step/ca-is3721hw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
e0570f476c6a89dd, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).