component
CA-IS3721HG
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-8-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IS3721HG
Chipanalog · Digital Isolators · SOIC-8-300mil
CA-IS3721HG from Chipanalog, in a SOIC-8-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A power supply, operating range 2.375 V to 5.5 V relative to GNDA, with a 0.1 µF to 1 µF bypass capacitor. |
| 2 | VI1 | input | Side A digital input for channel 1, which is transmitted to VO1 on side B (CA-IS3721). |
| 3 | VO2 | output | Side A digital output for channel 2, which follows VI2 from side B (CA-IS3721); output drive is 4 mA at 5 V and defaults high on the H version when input power or signal is lost. |
| 4 | GNDA | power_in | Side A ground, the ground reference for VDDA and the side A signals. |
| 5 | GNDB | power_in | Side B ground, the ground reference for VDDB and the side B signals. |
| 6 | VI2 | input | Side B digital input for channel 2, which is transmitted to VO2 on side A (CA-IS3721). |
| 7 | VO1 | output | Side B digital output for channel 1, which follows VI1 from side A (CA-IS3721); output drive is 4 mA at 5 V and defaults high on the H version when input power or signal is lost. |
| 8 | VDDB | power_in | Side B power supply, operating range 2.375 V to 5.5 V relative to GNDB, with a 0.1 µF to 1 µF bypass capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8-300mil |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDDA, VDDB | -0.5 | 6 | V | 5 | ||
| Voltage at Ax, Bx, ENx | Vin | -0.5 | V | max VDDA+0.5, must not exceed 6 V | 5 | ||
| Output Current | IO | -20 | 20 | mA | 5 | ||
| Junction Temperature | TJ | 150 | °C | 5 | |||
| Storage Temperature | TSTG | -65 | 150 | °C | 5 | ||
| ESD HBM | VESD | -4000 | 4000 | V | HBM per ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| ESD CDM | VESD | -1000 | 1000 | V | CDM per JESD22-C101, all pins | 5 | |
| Supply Voltage | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | 5 | |
| VDD Undervoltage Threshold Rising | VDD(UVLO+) | 1.95 | 2.24 | 2.375 | V | Supply voltage rising | 5 |
| VDD Undervoltage Threshold Falling | VDD(UVLO-) | 1.88 | 2.1 | 2.325 | V | Supply voltage falling | 5 |
| UVLO Hysteresis | VHYS(UVLO) | 70 | 140 | 250 | mV | 5 | |
| High-level Output Current | IOH | -4 | mA | VDDO = 5V | 5 | ||
| High-level Output Current | IOH | -2 | mA | VDDO = 3.3V | 5 | ||
| High-level Output Current | IOH | -1 | mA | VDDO = 2.5V | 5 | ||
| Low-level Output Current | IOL | 4 | mA | VDDO = 5V | 5 | ||
| Low-level Output Current | IOL | 2 | mA | VDDO = 3.3V | 5 | ||
| Low-level Output Current | IOL | 1 | mA | VDDO = 2.5V | 5 | ||
| High-level Input Voltage | VIH | 2 | V | 5 | |||
| Low-level Input Voltage | VIL | 0.8 | V | 5 | |||
| Data Rate | DR | 0 | 150 | Mbps | 5 | ||
| Ambient Temperature | TA | -40 | 27 | 125 | °C | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 92.3 | °C/W | G (SOIC) 8 pins | 6 | ||
| Junction-to-case(top) thermal resistance | RθJC(top) | 45.3 | °C/W | G (SOIC) 8 pins | 6 | ||
| Junction-to-board thermal resistance | RθJB | 50.5 | °C/W | G (SOIC) 8 pins | 6 | ||
| Junction-to-top characterization parameter | ψJT | 14 | °C/W | G (SOIC) 8 pins | 6 | ||
| Junction-to-board characterization parameter | ψJB | 49.3 | °C/W | G (SOIC) 8 pins | 6 | ||
| Maximum Power Dissipation | PD | 120 | mW | CA-IS3721; VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, 75-MHz 50% duty cycle square wave | 6 | ||
| Maximum Power Dissipation on Side-A | PDA | 60 | mW | CA-IS3721 | 6 | ||
| Maximum Power Dissipation on Side-B | PDB | 60 | mW | CA-IS3721 | 6 | ||
| Maximum withstanding isolation voltage | VISO | 5000 | VRMS | UL 1577; VTEST = VISO, t = 60 s; G package | 7 | ||
| Maximum repetitive peak isolation voltage | VIORM | 1414 | VPK | AC voltage (bipolar); G package | 7 | ||
| Maximum transient isolation voltage | VIOTM | 7070 | VPK | VTEST = VIOTM, t = 60 s; G package | 7 | ||
| High-level Output Voltage | VOH | 4.8 | V | VDD = 5 V ±10%; IOH = -4mA; min VDDO-0.4 | 9 | ||
| High-level Output Voltage | VOH | 3.1 | V | VDD = 3.3 V ±10%; IOH = -4mA; min VDDO-0.4 | 9 | ||
| High-level Output Voltage | VOH | 2.3 | V | VDD = 2.5 V ±5%; IOH = -4mA; min VDDO-0.4 | 9 | ||
| Low-level Output Voltage | VOL | 0.2 | 0.4 | V | IOL = 4mA | 9 | |
| Positive-going Input Threshold | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | 9 | |
| Negative-going Input Threshold | VIT-(IN) | 1 | 1.23 | 1.4 | V | 9 | |
| Input Threshold Hysteresis | VI(HYS) | 0.3 | 0.44 | 0.5 | V | 9 | |
| High-Level Input Leakage Current | IIH | 4 | µA | VIH = VDDA at Ax or Bx or ENx | 9 | ||
| Low-Level Input Leakage Current | IIL | -4 | µA | VIL = 0 V at Ax or Bx | 9 | ||
| Output Impedance | ZO | 50 | Ω | 9 | |||
| Common-mode Transient Immunity | CMTI | 75 | 100 | kV/µS | VI = VDDI or 0 V, VCM = 1200 V | 9 | |
| Input Capacitance | CI | 2 | pF | VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5 V | 9 | ||
| Supply Current DC Signal Side A | IDDA | 1.3 | 2 | mA | CA-IS3721; VDD = 5 V ±10%; VIN = VDDI (CA-IS3721H) | 10 | |
| Supply Current DC Signal Side B | IDDB | 1.3 | 2 | mA | CA-IS3721; VDD = 5 V ±10%; VIN = VDDI (CA-IS3721H) | 10 | |
| Supply Current AC 100Mbps Side A | IDDA | 7 | 10.5 | mA | CA-IS3721; VDD = 5 V ±10%; 100Mbps (50MHz), CL = 15 pF each channel | 10 | |
| Supply Current AC 100Mbps Side B | IDDB | 7 | 10.5 | mA | CA-IS3721; VDD = 5 V ±10%; 100Mbps (50MHz), CL = 15 pF each channel | 10 | |
| Data Rate | DR | 0 | 150 | Mbps | 13 | ||
| Minimum Pulse Width | PWmin | 5 | ns | 13 | |||
| Propagation Delay Time | tPLH, tPHL | 5 | 8 | 13 | ns | See Figure 7-1 | 13 |
| Pulse Width Distortion /tPLH - tPHL/ | PWD | 0.2 | 4.5 | ns | VDD = 5 V and 3.3 V; 2.5 V max 5.0 | 13 | |
| Channel-to-channel Output Skew Time | tsk(o) | 0.4 | 2.5 | ns | Same-direction | 13 | |
| Part-to-part Skew Time | tsk(pp) | 2 | 4.5 | ns | VDD = 5 V and 3.3 V; 2.5 V max 5.0 | 13 | |
| Output Signal Rise Time | tr | 2.5 | 4 | ns | See Figure 7-1 | 13 | |
| Output Signal Fall Time | tf | 2.5 | 4 | ns | See Figure 7-1 | 13 | |
| Default Output Delay Time from Input Power Loss | tDO | 8 | 12 | ns | See Figure 7-2 | 13 | |
| Start-up Time | tSU | 15 | 40 | µs | 13 | ||
| Pulse Width Distortion 2.5 V | PWD | 0.2 | 5 | ns | VDDA = VDDB = 2.5 V ±5% | 13 |
CAD (KiCad official)
- Symbol:
CA-IS3721HG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is3721hg-etched.step/ca-is3721hg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3721hg.step/ca-is3721hg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (22 pp, sha256
39fb33a8351462e1, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).