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CA-IS3720HW

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Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3720HW

Chipanalog · Digital Isolators · SOIC-16-300mil

CA-IS3720HW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GNDA power_in Side A ground reference.
2 NC unconnected No internal connection; may be left floating, tied to VDD or tied to GND.
3 VDDA power_in Side A supply voltage (2.375 V to 5.5 V recommended), with a 0.1 µF to 1 µF bypass capacitor.
4 VI1 input Side A logic input for channel 1 (CA-IS3720 forward channel).
5 VI2 input Side A logic input for channel 2 (CA-IS3720 forward channel).
6 NC unconnected No internal connection; may be left floating, tied to VDD or tied to GND.
7 GNDA power_in Side A ground reference.
8 NC unconnected No internal connection; may be left floating, tied to VDD or tied to GND.
9 GNDB power_in Side B ground reference.
10 NC unconnected No internal connection; may be left floating, tied to VDD or tied to GND.
11 NC unconnected No internal connection; may be left floating, tied to VDD or tied to GND.
12 VO2 output Side B logic output for channel 2; defaults high on loss of input power or signal (H suffix).
13 VO1 output Side B logic output for channel 1; defaults high on loss of input power or signal (H suffix).
14 VDDB power_in Side B supply voltage (2.375 V to 5.5 V recommended), with a 0.1 µF to 1 µF bypass capacitor.
15 NC unconnected No internal connection; may be left floating, tied to VDD or tied to GND.
16 GNDB power_in Side B ground reference.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-16-300mil
Category Signal Isolation Devices
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VDDA, VDDB) VDDA, VDDB 2.375 3.3 5.5 V 6
Undervoltage threshold, rising VDD VDD(UVLO+) 1.95 2.24 2.375 V 6
Undervoltage threshold, falling VDD VDD(UVLO-) 1.88 2.1 2.325 V 6
Undervoltage threshold hysteresis VHYS(UVLO) 70 140 250 mV 6
High-level output current IOH -4 mA VDDO = 5V 6
High-level output current IOH -2 mA VDDO = 3.3V 6
High-level output current IOH -1 mA VDDO = 2.5V 6
Low-level output current IOL 4 mA VDDO = 5V 6
Low-level output current IOL 2 mA VDDO = 3.3V 6
Low-level output current IOL 1 mA VDDO = 2.5V 6
Input threshold logic high VIH 2 V 6
Input threshold logic low VIL 0.8 V 6
Signaling data rate DR 0 150 Mbps 6
Ambient temperature TA -40 27 125 °C 6
Supply voltage (VDDA, VDDB) VDDA, VDDB -0.5 6 V Relative to local GND (GNDA or GNDB) 6
Input voltage Ax, Bx, ENx Vin -0.5 V Ax, Bx, ENx 6
Output current IO -20 20 mA 6
Junction temperature TJ 150 °C 6
Storage temperature range TSTG -65 150 °C 6
Maximum power dissipation (CA-IS3720) PD 120 mW VDDA = VDDB = 5.5V, CL = 15pF, TJ = 150°C, 75MHz 50% duty square-wave input 7
Maximum power dissipation, A side (CA-IS3720) PDA 20 mW VDDA = VDDB = 5.5V, CL = 15pF, TJ = 150°C, 75MHz 50% duty square-wave input 7
Maximum power dissipation, B side (CA-IS3720) PDB 100 mW VDDA = VDDB = 5.5V, CL = 15pF, TJ = 150°C, 75MHz 50% duty square-wave input 7
Output voltage logic low VOL 0.2 0.4 V VDDA = VDDB = 5V ±10%; IOL = 4mA; Fig 8-1 10
Positive input threshold VIT+(IN) 1.4 1.67 1.9 V VDDA = VDDB = 5V ±10% 10
Negative input threshold VIT-(IN) 1 1.23 1.4 V VDDA = VDDB = 5V ±10% 10
Input threshold hysteresis VI(HYS) 0.3 0.44 0.5 V VDDA = VDDB = 5V ±10% 10
Input high-level leakage current IIH 4 µA VIH = VDDA at Ax or Bx or ENx; VDDA = VDDB = 5V ±10% 10
Input low-level leakage current IIL -4 µA VIL = 0 V at Ax or Bx; VDDA = VDDB = 5V ±10% 10
Common-mode transient immunity CMTI 75 100 kV/µs VI = VDDI1 or 0 V, VCM = 1200 V; Fig 8-3; VDDA = VDDB = 5V ±10% 10
Output voltage logic high VOH 4.8 V IOH = -4mA; Fig 8-1; VDDA = VDDB = 5V ±10% 10
Output impedance ZO 50 Ω VDDA = VDDB = 5V ±10% 10
Input capacitance CI 2 pF VI = VDD/2 + 0.4×sin(2πft), f = 1 MHz, VDD = 5V 10
Output voltage logic high VOH 3.1 V IOH = -4mA; Fig 8-1; VDDA = VDDB = 3.3V ±10% 10
Output voltage logic high VOH 2.3 V IOH = -4mA; Fig 8-1; VDDA = VDDB = 2.5V ±5% 10
Junction-to-ambient thermal resistance RθJA 86.5 °C/W W package, 16 pins 7
Junction-to-case (top) thermal resistance RθJC(top) 49.6 °C/W W package, 16 pins 7
Junction-to-board thermal resistance RθJB 49.7 °C/W W package, 16 pins 7
Junction-to-top characterization parameter ψJT 32.3 °C/W W package, 16 pins 7
Junction-to-board characterization parameter ψJB 49.2 °C/W W package, 16 pins 7

CAD (KiCad official)

  • Symbol: CA-IS3720HW
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ca-is3720hw-etched.step / ca-is3720hw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3720hw.step / ca-is3720hw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (25 pp, sha256 e0570f476c6a89dd, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF