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CA-IS3720HS
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Chipanalog Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownCA-IS3720HS
Chipanalog · Digital Isolators · SOIC-8
CA-IS3720HS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | A-side supply voltage; recommended operating range is 2.375 V to 5.5 V, and the absolute maximum is 6.0 V referenced to GNDA. |
| 2 | VI1 | input | A-side logic input of channel 1 with Schmitt-trigger thresholds (VIH 2.0 V min, VIL 0.8 V max); input voltage must stay between -0.5 V and VDDA+0.5 V (absolute maximum, not to exceed 6 V). |
| 3 | VI2 | input | A-side logic input of channel 2 with Schmitt-trigger thresholds (VIH 2.0 V min, VIL 0.8 V max); input voltage must stay between -0.5 V and VDDA+0.5 V (absolute maximum, not to exceed 6 V). |
| 4 | GNDA | power_in | A-side ground reference; all A-side signals and VDDA are referenced to this pin and it is isolated from GNDB. |
| 5 | GNDB | power_in | B-side ground reference for VDDB and the B-side outputs, isolated from GNDA by the isolation barrier. |
| 6 | VO2 | output | B-side logic output of channel 2 following VI2; rated IOH of -4 mA at VDDO = 5 V (-2 mA at 3.3 V, -1 mA at 2.5 V) and IOL of 4 mA at 5 V, with default output state set by the H suffix (high) on input power loss. |
| 7 | VO1 | output | B-side logic output of channel 1 following VI1; rated IOH of -4 mA at VDDO = 5 V (-2 mA at 3.3 V, -1 mA at 2.5 V) and IOL of 4 mA at 5 V, with default output state set by the H suffix (high) on input power loss. |
| 8 | VDDB | power_in | B-side supply voltage; recommended operating range is 2.375 V to 5.5 V, and the absolute maximum is 6.0 V referenced to GNDB. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDDA, VDDB (recommended) | VDDA, VDDB | 2.375 | 3.3 | 5.5 | V | 6 | |
| UVLO threshold, rising VDD | VDD（UVLO+） | 1.95 | 2.24 | 2.375 | V | 6 | |
| UVLO threshold, falling VDD | VDD（UVLO-） | 1.88 | 2.1 | 2.325 | V | 6 | |
| UVLO hysteresis | VHYS（UVLO） | 70 | 140 | 250 | mV | 6 | |
| High-level output current | IOH | -4 | mA | VDDO = 5V | 6 | ||
| High-level output current | IOH | -2 | mA | VDDO = 3.3V | 6 | ||
| High-level output current | IOH | -1 | mA | VDDO = 2.5V | 6 | ||
| Low-level output current | IOL | 4 | mA | VDDO = 5V | 6 | ||
| Low-level output current | IOL | 2 | mA | VDDO = 3.3V | 6 | ||
| Low-level output current | IOL | 1 | mA | VDDO = 2.5V | 6 | ||
| Input threshold logic high | VIH | 2 | V | 6 | |||
| Input threshold logic low | VIL | 0.8 | V | 6 | |||
| Signal data rate | DR | 0 | 150 | Mbps | 6 | ||
| Ambient temperature | TA | -40 | 27 | 125 | °C | 6 | |
| Supply voltage VDDA, VDDB (absolute maximum) | VDDA, VDDB | -0.5 | 6 | V | 6 | ||
| Input voltage Ax, Bx, ENx (absolute maximum) | Vin | -0.5 | V | 6 | |||
| Output current (absolute maximum) | IO | -20 | 20 | mA | 6 | ||
| Junction temperature (absolute maximum) | TJ | 150 | °C | 6 | |||
| Storage temperature range (absolute maximum) | TSTG | -65 | 150 | °C | 6 | ||
| Junction-to-ambient thermal resistance, SOIC-8 (S) | RθJA | 137.7 | °C/W | 7 | |||
| Junction-to-case (top) thermal resistance, SOIC-8 (S) | RθJC(top) | 54.9 | °C/W | 7 | |||
| Junction-to-board thermal resistance, SOIC-8 (S) | RθJB | 71.7 | °C/W | 7 | |||
| High-level output voltage (VDDA=VDDB=5V) | VOH | 4.8 | V | IOH = -4mA; 图 8-1 | 10 | ||
| Low-level output voltage (VDDA=VDDB=5V) | VOL | 0.2 | 0.4 | V | IOL = 4mA; 图 8-1 | 10 | |
| Positive input threshold (VDDA=VDDB=5V) | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | 10 | |
| Negative input threshold (VDDA=VDDB=5V) | VIT-(IN) | 1 | 1.23 | 1.4 | V | 10 | |
| Input threshold hysteresis (VDDA=VDDB=5V) | VI(HYS) | 0.3 | 0.44 | 0.5 | V | 10 | |
| Input high-level leakage current (VDDA=VDDB=5V) | IIH | 4 | µA | VIH = VDDA at Ax or Bx or ENx | 10 | ||
| Input low-level leakage current (VDDA=VDDB=5V) | IIL | -4 | µA | VIL = 0 V at Ax or Bx | 10 | ||
| Common-mode transient immunity (VDDA=VDDB=5V) | CMTI | 75 | 100 | kV/µS | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 10 | |
| High-level output voltage (VDDA=VDDB=3.3V) | VOH | 3.1 | V | IOH = -4mA; 图 8-1 | 10 | ||
| Low-level output voltage (VDDA=VDDB=3.3V) | VOL | 0.2 | 0.4 | V | IOL = 4mA; 图 8-1 | 10 | |
| Positive input threshold (VDDA=VDDB=3.3V) | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | 10 | |
| Negative input threshold (VDDA=VDDB=3.3V) | VIT-(IN) | 1 | 1.23 | 1.4 | V | 10 | |
| Input threshold hysteresis (VDDA=VDDB=3.3V) | VI(HYS) | 0.3 | 0.44 | 0.5 | V | 10 | |
| Input high-level leakage current (VDDA=VDDB=3.3V) | IIH | 4 | µA | VIH = VDDA at Ax or Bx or ENx | 10 | ||
| Input low-level leakage current (VDDA=VDDB=3.3V) | IIL | -4 | µA | VIL = 0 V at Ax or Bx | 10 | ||
| Common-mode transient immunity (VDDA=VDDB=3.3V) | CMTI | 75 | 100 | kV/µs | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 10 | |
| High-level output voltage (VDDA=VDDB=2.5V) | VOH | 2.3 | V | IOH = -4mA; 图 8-1 | 10 | ||
| Low-level output voltage (VDDA=VDDB=2.5V) | VOL | 0.2 | 0.4 | V | IOL = 4mA; 图 8-1 | 10 | |
| Positive input threshold (VDDA=VDDB=2.5V) | VIT+(IN) | 1.4 | 1.67 | 1.9 | V | 10 | |
| Negative input threshold (VDDA=VDDB=2.5V) | VIT-(IN) | 1 | 1.23 | 1.4 | V | 10 | |
| Input threshold hysteresis (VDDA=VDDB=2.5V) | VI(HYS) | 0.3 | 0.44 | 0.5 | V | 10 | |
| Input high-level leakage current (VDDA=VDDB=2.5V) | IIH | 4 | µA | VIH = VDDA at Ax or Bx or ENx | 10 | ||
| Input low-level leakage current (VDDA=VDDB=2.5V) | IIL | -4 | µA | VIL = 0 V at Ax or Bx | 10 | ||
| Common-mode transient immunity (VDDA=VDDB=2.5V) | CMTI | 75 | 100 | kV/µS | VI = VDDI1 or 0 V, VCM = 1200 V; 图 8-3 | 10 | |
| DC supply current IDDA, CA-IS3720H (VDDA=VDDB=5V) | IDDA | 0.8 | 1.2 | mA | VIN = 0V (CA-IS3720L); VIN = VDDI (CA-IS3720H) | 11 | |
| DC supply current IDDB, CA-IS3720H (VDDA=VDDB=5V) | IDDB | 1.6 | 2.3 | mA | VIN = 0V (CA-IS3720L); VIN = VDDI (CA-IS3720H) | 11 | |
| DC supply current IDDA, CA-IS3720H (VDDA=VDDB=5V) | IDDA | 2.3 | 3.5 | mA | VIN = VDDI (CA-IS3720L); VIN = 0V (CA-IS3720H) | 11 | |
| DC supply current IDDB, CA-IS3720H (VDDA=VDDB=5V) | IDDB | 1.6 | 2.4 | mA | VIN = VDDI (CA-IS3720L); VIN = 0V (CA-IS3720H) | 11 | |
| Pulse width minimum (VDDA=VDDB=5V) | PWmin | 5 | ns | 14 | |||
| Propagation delay tPLH, tPHL (VDDA=VDDB=5V) | tPLH, tPHL | 5 | 8 | 13 | ns | 图 8-1 | 14 |
| Pulse width distortion (VDDA=VDDB=5V) | PWD | 0.2 | 4.5 | ns | /tPLH - tPHL/ | 14 | |
| Channel-to-channel output skew (VDDA=VDDB=5V) | tsk(o) | 0.4 | 2.5 | ns | 同方向通道 | 14 | |
| Part-to-part skew (VDDA=VDDB=5V) | tsk(pp) | 2 | 4.5 | ns | 14 | ||
| Output rise time (VDDA=VDDB=5V) | tr | 2.5 | 4 | ns | 图 8-1 | 14 | |
| Output fall time (VDDA=VDDB=5V) | tf | 2.5 | 4 | ns | 图 8-1 | 14 | |
| Default output delay from input power loss (VDDA=VDDB=5V) | tDO | 8 | 12 | ns | 图 8-2 | 14 | |
| Startup time (VDDA=VDDB=5V) | tSU | 15 | 40 | µs | 14 |
CAD (KiCad official)
- Symbol:
CA-IS3720HS - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ca-is3720hs-etched.step/ca-is3720hs-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3720hs.step/ca-is3720hs.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (25 pp, sha256
e0570f476c6a89dd, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).