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CA-IS3720CHS

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Chipanalog Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IS3720CHS

Chipanalog · Digital Isolators · SOIC-8

CA-IS3720CHS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDA power_in A-side supply voltage, recommended range 3.0 V to 5.5 V (typ. 3.3 V), with 0.1 µF and 1 µF bypass capacitors placed close to the pin.
2 VI1 input Channel 1 A-side logic input of the CA-IS3720C, CMOS-compatible Schmitt-trigger input with VIH ≥ 0.7 × VDDI and VIL ≤ 0.3 × VDDI.
3 VI2 input Channel 2 A-side logic input of the CA-IS3720C, CMOS-compatible Schmitt-trigger input with VIH ≥ 0.7 × VDDI and VIL ≤ 0.3 × VDDI.
4 GNDA power_in A-side ground reference; all voltages on this side are referenced to GNDA.
5 GNDB power_in B-side ground reference; all voltages on this side are referenced to GNDB.
6 VO2 output Channel 2 B-side logic output of the CA-IS3720C, rated IOH −4 mA and IOL 4 mA at VDDO = 5 V (−2 mA / 2 mA at 3.3 V); defaults high on input-side power loss for the H variant.
7 VO1 output Channel 1 B-side logic output of the CA-IS3720C, rated IOH −4 mA and IOL 4 mA at VDDO = 5 V (−2 mA / 2 mA at 3.3 V); defaults high on input-side power loss for the H variant.
8 VDDB power_in B-side supply voltage, recommended range 3.0 V to 5.5 V (typ. 3.3 V), with 0.1 µF and 1 µF bypass capacitors placed close to the pin.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDDA, VDDB -0.5 7 V 6
Output current IO -20 20 mA 6
Junction temperature TJ 150 °C 6
Storage temperature range TSTG -65 150 °C 6
Input voltage VIN -0.5 V 6
Supply voltage VDDA, VDDB 3 3.3 5.5 V 6
VDD undervoltage threshold, rising VDD(UVLO+) 2.55 2.7 2.85 V 6
VDD undervoltage threshold, falling VDD(UVLO-) 2.35 2.5 2.65 V 6
VDD undervoltage hysteresis VHYS(UVLO) 150 200 270 mV 6
High-level output current IOH -4 mA VDDO1 = 5V 6
High-level output current IOH -2 mA VDDO1 = 3.3V 6
Low-level output current IOL 4 mA VDDO1 = 5V 6
Low-level output current IOL 2 mA VDDO1 = 3.3V 6
Input threshold logic low VIL 0 V 6
Signal data rate DR 0 40 Mbps 6
Ambient temperature TA -40 27 125 °C 6
Maximum power dissipation PD 60 mW VDDA = VDDB = 5.5V, CL = 15pF, TJ = 150°C, input 20MHz 50% duty square wave 7
Maximum power dissipation, A side PDA 20 mW VDDA = VDDB = 5.5V, CL = 15pF, TJ = 150°C, input 20MHz 50% duty square wave 7
Maximum power dissipation, B side PDB 40 mW VDDA = VDDB = 5.5V, CL = 15pF, TJ = 150°C, input 20MHz 50% duty square wave 7
Output voltage logic low VOL 0.2 0.4 V VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; IOL = 4mA; Fig 8-1 10
Input high leakage current IIH 20 µA VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; VIH = VDDI1 at VIx 10
Input low leakage current IIL -20 µA VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; VIL = 0V at VIx 10
Common-mode transient immunity CMTI 100 150 kV/µs VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; VI = VDDI1 or 0V, VCM = 1200V; Fig 8-3 10
Minimum pulse width PWmin 20 ns VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C 13
Propagation delay tPLH, tPHL 22 35 ns VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; Fig 8-1 13
Pulse width distortion PWD 2.5 7 ns VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; /tPLH - tPHL/ 13
Channel-to-channel output skew, same direction tsk(o) 1 3 ns VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C 13
Part-to-part channel output skew tsk(pp) 1 7 ns VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C 13
Output rise time tr 2.5 4.8 ns VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; Fig 8-1 13
Output fall time tf 2.5 4.8 ns VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; Fig 8-1 13
Default output delay from input power down tDO 10 15 ns VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C; Fig 8-2 13
Start-up time tSU 25 37 µs VDDA = VDDB = 5V ± 10%, TA = -40 to 125°C 13
Pulse width distortion PWD 3 7 ns VDDA = VDDB = 3.3V ± 10%, TA = -40 to 125°C; /tPLH - tPHL/ 13
Supply current, side A, DC IDDA 1 2.1 mA VDDA = VDDB = 5V ± 10%; VIN = 0V (CA-IS3720CL); VIN = VDDI1 (CA-IS3720CH) 11
Supply current, side B, DC IDDB 2.9 5 mA VDDA = VDDB = 5V ± 10%; VIN = 0V (CA-IS3720CL); VIN = VDDI1 (CA-IS3720CH) 11
Supply current, side A, DC IDDA 3.8 6.3 mA VDDA = VDDB = 5V ± 10%; VIN = VDDI1 (CA-IS3720CL); VIN = 0V (CA-IS3720CH) 11
Supply current, side B, DC IDDB 3.1 5.3 mA VDDA = VDDB = 5V ± 10%; VIN = VDDI1 (CA-IS3720CL); VIN = 0V (CA-IS3720CH) 11
Supply current, side A, 1Mbps IDDA 2.5 4.4 mA VDDA = VDDB = 5V ± 10%; all inputs 50% duty square wave 5V; CL = 15pF per channel; 1Mbps (500kHz) 11
Supply current, side B, 1Mbps IDDB 3.1 5.3 mA VDDA = VDDB = 5V ± 10%; all inputs 50% duty square wave 5V; CL = 15pF per channel; 1Mbps (500kHz) 11
Supply current, side A, 10Mbps IDDA 3 5.1 mA VDDA = VDDB = 5V ± 10%; all inputs 50% duty square wave 5V; CL = 15pF per channel; 10Mbps (5MHz) 11
Supply current, side B, 10Mbps IDDB 3.9 6.5 mA VDDA = VDDB = 5V ± 10%; all inputs 50% duty square wave 5V; CL = 15pF per channel; 10Mbps (5MHz) 11
Supply current, side A, 40Mbps IDDA 3.4 5.7 mA VDDA = VDDB = 5V ± 10%; all inputs 50% duty square wave 5V; CL = 15pF per channel; 40Mbps (20MHz) 11
Supply current, side B, 40Mbps IDDB 6.5 10.4 mA VDDA = VDDB = 5V ± 10%; all inputs 50% duty square wave 5V; CL = 15pF per channel; 40Mbps (20MHz) 11
Supply current, side A, DC IDDA 1 2.1 mA VDDA = VDDB = 3.3V ± 10%; VIN = 0V (CA-IS3720CL); VIN = VDDI1 (CA-IS3720CH) 12
Supply current, side B, DC IDDB 2.8 4.8 mA VDDA = VDDB = 3.3V ± 10%; VIN = 0V (CA-IS3720CL); VIN = VDDI1 (CA-IS3720CH) 12
Supply current, side A, DC IDDA 3.7 6.2 mA VDDA = VDDB = 3.3V ± 10%; VIN = VDDI1 (CA-IS3720CL); VIN = 0V (CA-IS3720CH) 12
Supply current, side B, DC IDDB 3 5.1 mA VDDA = VDDB = 3.3V ± 10%; VIN = VDDI1 (CA-IS3720CL); VIN = 0V (CA-IS3720CH) 12
Thermal resistance, junction to ambient (SOIC8-NB, S) RθJA 109 °C/W 7

CAD (KiCad official)

  • Symbol: CA-IS3720CHS
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ca-is3720chs-etched.step / ca-is3720chs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-is3720chs.step / ca-is3720chs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (24 pp, sha256 24fee350c7266eeb, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF