CA-IS3644HVW

{
  "schema_version": 1,
  "type": "component",
  "slug": "ca-is3644hvw",
  "title": "CA-IS3644HVW",
  "brief": "Chipanalog Digital Isolators (With Power), SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "signal isolation devices",
    "ca-is3644hvw"
  ],
  "component": {
    "mpn": "CA-IS3644HVW",
    "manufacturer": "Chipanalog",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Signal Isolation Devices",
    "subcategory": "Digital Isolators (With Power)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590235090224910336",
    "parts": {
      "symbol": "ca-is3644hvw.kicad_sym",
      "footprint": "ca-is3644hvw.kicad_mod",
      "model_3d": "ca-is3644hvw-etched.glb",
      "model_3d_plain": "ca-is3644hvw.glb",
      "model_3d_step": "ca-is3644hvw-etched.step",
      "model_3d_step_plain": "ca-is3644hvw.step",
      "lbr": "ca-is3644hvw.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "A-side power supply for the internal DC-DC converter primary (3.15 V to 5.5 V). Bypass to GNDA with 0.1 uF and 10 uF placed within 2 mm of the pin."
      },
      {
        "number": "2",
        "name": "GNDA",
        "type": "power_in",
        "description": "A-side ground reference."
      },
      {
        "number": "3",
        "name": "VO1",
        "type": "output",
        "description": "Channel 1 A-side logic output (receives data from B-side input VI1 on pin 14). Output level is set by VDDL. Default state HIGH on failure per the H suffix."
      },
      {
        "number": "4",
        "name": "VO2",
        "type": "output",
        "description": "Channel 2 A-side logic output (receives data from B-side input VI2 on pin 13). Output level is set by VDDL. Default state HIGH on failure."
      },
      {
        "number": "5",
        "name": "VO3",
        "type": "output",
        "description": "Channel 3 A-side logic output (receives data from B-side input VI3 on pin 12). Output level is set by VDDL. Default state HIGH on failure."
      },
      {
        "number": "6",
        "name": "VO4",
        "type": "output",
        "description": "Channel 4 A-side logic output (receives data from B-side input VI4 on pin 11). Output level is set by VDDL. Default state HIGH on failure."
      },
      {
        "number": "7",
        "name": "VDDL",
        "type": "power_in",
        "description": "A-side logic supply (2.375 V to 5.5 V). Sets the A-side input logic threshold and A-side output HIGH level. Present because this part is the 'V' variant (CA-IS3644HVW); on the non-V CA-IS3644HW this pin is NC."
      },
      {
        "number": "8",
        "name": "GNDA",
        "type": "power_in",
        "description": "A-side ground reference (second GNDA pin)."
      },
      {
        "number": "9",
        "name": "GNDB",
        "type": "power_in",
        "description": "B-side (isolated) ground reference."
      },
      {
        "number": "10",
        "name": "SEL",
        "type": "input",
        "description": "VISO output-voltage select. Tie to VISO for VISO = 5 V; tie to GNDB or leave floating for VISO = 3.3 V. Referenced to the B-side domain."
      },
      {
        "number": "11",
        "name": "VI4",
        "type": "input",
        "description": "Channel 4 B-side logic input; drives the A-side output VO4 on pin 6. Input threshold referenced to VISO (B-side domain)."
      },
      {
        "number": "12",
        "name": "VI3",
        "type": "input",
        "description": "Channel 3 B-side logic input; drives the A-side output VO3 on pin 5."
      },
      {
        "number": "13",
        "name": "VI2",
        "type": "input",
        "description": "Channel 2 B-side logic input; drives the A-side output VO2 on pin 4."
      },
      {
        "number": "14",
        "name": "VI1",
        "type": "input",
        "description": "Channel 1 B-side logic input; drives the A-side output VO1 on pin 3."
      },
      {
        "number": "15",
        "name": "GNDB",
        "type": "power_in",
        "description": "B-side (isolated) ground reference (second GNDB pin)."
      },
      {
        "number": "16",
        "name": "VISO",
        "type": "power_out",
        "description": "Isolated B-side output voltage generated by the internal DC-DC converter. 3.3 V or 5 V selected by the SEL pin. Bypass to GNDB with 0.1 uF and 10 uF placed within 2 mm of the pin. Supplies up to ~120 mA (5V/1Mbps) or ~80 mA at 100 Mbps depending on channel loading."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590235090224910336",
        "pages": 39,
        "sha256": "74e1e848c9ed7ac2",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ca-is3644hvw.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ca-is3644hvw-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "941287d8ff9c3017c9d4278e466bab938de16bd47dd33ea4ee9af9a6249389be",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Chipanalog",
      "Package": "SOIC-16",
      "Category": "Signal Isolation Devices",
      "Pins": "16"
    }
  },
  "variants": [
    {
      "mpn": "CA-IS3644HVW",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3644HVWLVW",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3644HVWHW",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3644HVWLW",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "ca-is3644hvw"
  ],
  "discovery_pitch": "CA-IS3644HVW (Chipanalog) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "ca-is3644hvw.kicad_sym",
    "ca-is3644hvw.kicad_mod",
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    "ca-is3644hvw.step",
    "ca-is3644hvw.lbr",
    "docs/hero.png",
    "docs/ca-is3644hvw-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T18:25:33.580Z"
}