CA-IS3642LVW

{
  "schema_version": 1,
  "type": "component",
  "slug": "ca-is3642lvw",
  "title": "CA-IS3642LVW",
  "brief": "Chipanalog Digital Isolators (With Power), SOIC-16-300mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "signal isolation devices",
    "ca-is3642lvw"
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  "component": {
    "mpn": "CA-IS3642LVW",
    "manufacturer": "Chipanalog",
    "package": "SOIC-16-300mil",
    "pin_count": 16,
    "category": "Signal Isolation Devices",
    "subcategory": "Digital Isolators (With Power)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602993959816359936",
    "parts": {
      "symbol": "ca-is3642lvw.kicad_sym",
      "footprint": "ca-is3642lvw.kicad_mod",
      "model_3d": "ca-is3642lvw-etched.glb",
      "model_3d_plain": "ca-is3642lvw.glb",
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      "model_3d_step_plain": "ca-is3642lvw.step",
      "lbr": "ca-is3642lvw.lbr"
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    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "VDD",
        "type": "power_in",
        "description": "A-side supply for the internal DC-DC converter primary. Range 3.15 V to 5.5 V (typ 5 V). Decouple to GNDA with 0.1 uF and 10 uF placed within 2 mm of the pin."
      },
      {
        "number": "2",
        "name": "GNDA",
        "type": "power_in",
        "description": "A-side ground reference."
      },
      {
        "number": "3",
        "name": "VI1",
        "type": "input",
        "description": "Forward channel 1: A-side logic input driving isolated output VO1 on pin 14. Input thresholds are referenced to VDDL on the LVW variant (VIH >= 2.0 V, VIL <= 0.8 V)."
      },
      {
        "number": "4",
        "name": "VI2",
        "type": "input",
        "description": "Forward channel 2: A-side logic input driving isolated output VO2 on pin 13. Referenced to GNDA/VDDL."
      },
      {
        "number": "5",
        "name": "VO3",
        "type": "output",
        "description": "Reverse channel 3: A-side logic output driven by isolated input VI3 on pin 12. Drive strength IOH = -4 mA / IOL = 4 mA at VDDO = 5 V."
      },
      {
        "number": "6",
        "name": "VO4",
        "type": "output",
        "description": "Reverse channel 4: A-side logic output driven by isolated input VI4 on pin 11. Drive strength IOH = -4 mA / IOL = 4 mA at VDDO = 5 V."
      },
      {
        "number": "7",
        "name": "VDDL",
        "type": "power_in",
        "description": "A-side logic supply that sets the input-threshold and output logic-high level for VI1/VI2/VO3/VO4. Allows the A-side digital interface to run at a rail different from VDD (2.375 V to 5.5 V). Decouple to GNDA. Present on the LVW/VW-suffix variants (V = VDDL pinout)."
      },
      {
        "number": "8",
        "name": "GNDA",
        "type": "power_in",
        "description": "Second A-side ground reference; tie to pin 2 (same net)."
      },
      {
        "number": "9",
        "name": "GNDB",
        "type": "power_in",
        "description": "B-side (isolated) ground reference."
      },
      {
        "number": "10",
        "name": "SEL",
        "type": "input",
        "description": "VISO output-voltage select. Tie SEL to VISO (pin 16) for VISO = 5 V; tie to GNDB or leave floating for VISO = 3.3 V. Referenced to GNDB."
      },
      {
        "number": "11",
        "name": "VI4",
        "type": "input",
        "description": "Reverse channel 4: B-side logic input driving isolated output VO4 on pin 6. Referenced to GNDB/VISO."
      },
      {
        "number": "12",
        "name": "VI3",
        "type": "input",
        "description": "Reverse channel 3: B-side logic input driving isolated output VO3 on pin 5. Referenced to GNDB/VISO."
      },
      {
        "number": "13",
        "name": "VO2",
        "type": "output",
        "description": "Forward channel 2: B-side logic output driven by isolated input VI2 on pin 4. Powered from VISO; on loss-of-signal defaults LOW (LVW fail-safe)."
      },
      {
        "number": "14",
        "name": "VO1",
        "type": "output",
        "description": "Forward channel 1: B-side logic output driven by isolated input VI1 on pin 3. Powered from VISO; default-low fail-safe on the L-suffix variant."
      },
      {
        "number": "15",
        "name": "GNDB",
        "type": "power_in",
        "description": "Second B-side ground reference; tie to pin 9 (same net)."
      },
      {
        "number": "16",
        "name": "VISO",
        "type": "power_out",
        "description": "Isolated output voltage generated by the internal DC-DC converter (secondary side). Selectable 3.3 V or 5 V via SEL; up to 650 mW output power. Decouple to GNDB with 0.1 uF and 10 uF placed within 2 mm of the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602993959816359936",
        "pages": 39,
        "sha256": "74e1e848c9ed7ac2",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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    "models_3d": [
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        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
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        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Chipanalog",
      "Package": "SOIC-16-300mil",
      "Category": "Signal Isolation Devices",
      "Pins": "16"
    }
  },
  "variants": [
    {
      "mpn": "CA-IS3642LVW",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3642LVWHVW",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3642LVWLW",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3642LVWHW",
      "kind": "packaging"
    }
  ],
  "sections": [
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  "discovery_triggers": [
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  "discovery_pitch": "CA-IS3642LVW (Chipanalog) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
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  "visibility": {
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  "updated_at": "2026-09-24T18:25:25.125Z"
}