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CA-IS3092VW
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Chipanalog Isolated RS-485/422 Transceivers With Power, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdownCA-IS3092VW
Chipanalog · Isolated RS-485/422 Transceivers With Power · SOIC-16-300mil
CA-IS3092VW from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Logic-side supply that powers the internal DC-DC converter and, on the VW version, is decoupled with 0.1 µF and 10 µF capacitors placed within 2 mm of the pin; recommended range 3.15 V to 5.5 V. |
| 2 | GNDA | power_in | Logic-side ground and the reference point for logic-side signals (also pin 8). |
| 3 | RO | output | Receiver data output, which goes high-impedance when the receiver is disabled (RE high), per truth table 9-1. |
| 4 | RE | input | Active-low receiver enable: low enables the receiver, high disables it and puts RO in high-impedance, and it is weakly pulled up internally to VCCL on the VW version. |
| 5 | DE | input | Active-high driver enable: high enables the driver, low puts the driver outputs in high-impedance, and it is weakly pulled down internally to GNDA. |
| 6 | DI | input | Driver data input: with DE high, DI high drives A high and B low, and DI low drives A low and B high; it is weakly pulled up internally to VCCL on the VW version. |
| 7 | VCCL | power_in | Logic-side RS-485 supply that sets the logic input thresholds and output levels on the VW version, with a recommended range of 2.375 V to 5.5 V and a 1 µF bypass capacitor to GNDA. |
| 8 | GNDA | power_in | Logic-side ground and the reference point for logic-side signals (also pin 2). |
| 9 | GNDB | power_in | Bus-side ground and the reference point for the RS-485 bus signals (also pin 15). |
| 10 | SEL | input | VISO output voltage select: tie to VISO for 5 V output, or tie to GNDB or leave floating for 3.3 V output, and it must be set before start-up and not changed during start-up (with VCC at 3.3 V, SEL must be GNDB or floating). |
| 11 | NC | unconnected | No internal connection on the VW version. |
| 12 | A | bidirectional | RS-485 bus non-inverting receiver input and driver non-inverting output. |
| 13 | B | bidirectional | RS-485 bus inverting receiver input and driver inverting output. |
| 14 | VISOIN | power_in | Bus-side RS-485 supply that sets the bus-side input thresholds and output levels, and must be shorted externally to the VISO pin (absolute maximum 6 V). |
| 15 | GNDB | power_in | Bus-side ground and the reference point for the RS-485 bus signals (also pin 9). |
| 16 | VISO | power_out | Isolated power output that supplies the bus side at 3.3 V or 5 V (selected by SEL), decoupled with 0.1 µF and 10 µF capacitors to GNDB placed within 2 mm of the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Signal Isolation Devices |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 逻辑侧电源电压 VCC，VCCL | VCC, VCCL | -0.5 | 6 | V | 6 | ||
| 总线侧电源电压 VISO，VISOIN | VISO, VISOIN | -0.5 | 6 | V | 6 | ||
| 逻辑侧端口电压 DE，DI，RE | VIO1 | -0.5 | V | 6 | |||
| 总线侧端口电压 SEL | VIO2 | -0.5 | V | 6 | |||
| 总线侧端口电压 A，B | VBUS | -8 | 13 | V | 6 | ||
| 输出电流 | IO | -20 | 20 | mA | 6 | ||
| 结温 | TJ | 150 | °C | 6 | |||
| 存储温度范围 | TSTG | -65 | 150 | °C | 6 | ||
| 逻辑侧电源电压 | VCC1 | 3.15 | 5.5 | V | 6 | ||
| 逻辑侧 RS-485 电源电压 | VCCL | 2.375 | 5.5 | V | 6 | ||
| A,B 引脚电压 | VOC | -7 | 12 | V | 6 | ||
| A,B 差分输入电压 | VID | -12 | 12 | V | 6 | ||
| 差分负载电阻 | RL | 54 | Ω | 6 | |||
| DE,DI 输入阈值逻辑高电平 | VIH | 2 | V | 6 | |||
| DE,DI 输入阈值逻辑低电平 | VIL | -0.3 | 0.8 | V | 6 | ||
| RE输入阈值逻辑低电平 | VIL | -0.3 | V | 6 | |||
| 信号传输速率 CA-IS3092 | DR | 0.5 | Mbps | 6 | |||
| 环境温度 | TA | -40 | 125 | °C | 6 | ||
| 差分输出电压（无负载） | /VOD1/ | 2.9 | V | IO = 0mA，SEL 为低电平或悬空 | 9 | ||
| 差分输出电压（无负载） | /VOD1/ | 3.7 | 4.6 | V | IO = 0mA，SEL 为高电平 | 9 | |
| 差分输出电压（带负载） | /VOD2/ | 1.5 | 2 | V | RL = 54Ω，SEL 为低电平或悬空；见图 8-1 | 9 | |
| 差分输出电压（带负载） | /VOD2/ | 2.1 | 3.6 | V | RL = 54Ω，SEL 为高电平；见图 8-1 | 9 | |
| 差分输出电压（带负载） | /VOD3/ | 1.5 | V | Vtest 从-7V 到 12V；见图 8-1 | 9 | ||
| 差分输出电压变化 | Δ/VOD/ | -0.2 | 0.2 | V | RL = 54Ω 或 100Ω；见图 8-1 | 9 | |
| 稳态共模输出电压变化 | ΔVOC | -0.2 | 0.2 | V | 9 | ||
| 输入漏电流 | IIH,IIL | -20 | 20 | µA | DI，DE = 0V 或 VCC | 9 | |
| 驱动器输出短路电流 | IOS | -150 | 150 | mA | DE = VCC, DI = 0V 或 VCC, VA 或 VB = -7V / 12V | 9 | |
| 共模瞬变抗扰度 | CMTI | 100 | 150 | kV/µs | VCM = 1.5kV；如图 8-6 | 9 | |
| 逻辑低电平输出电压 RO | VOL | 0.2 | 0.4 | V | VCC=5V，IOL = 4mA | 9 | |
| 高电平输入漏电流 RE | IIH | -20 | 20 | µA | VIH = VCC | 9 | |
| 低电平输入漏电流 RE | IIL | -20 | 20 | µA | VIL = 0V | 9 | |
| 高电平输入阈值 | VTH+ | -110 | -50 | mV | 9 | ||
| 低电平输入阈值 | VTH- | -200 | -140 | mV | 9 | ||
| 输入阈值迟滞 | VTH(HYS) | 30 | mV | 9 | |||
| 总线输入电流 | II | 75 | 125 | µA | VA 或 VB = 12V，其它输入引脚接 0V | 9 | |
| 总线输入电流 | II | 80 | 125 | µA | VA 或 VB = 12V, VCC = 0V，其它输入引脚接 0V | 9 | |
| 总线输入电流 | II | -100 | -40 | µA | VA 或 VB = -7V，其它输入引脚接 0V | 9 | |
| 隔离输出电压 | VISO | 4.75 | 5 | 5.25 | V | IISO = 0 到 130mA，VCC = 5V，SEL = GNDB 或 VISO | 10 |
| 隔离输出电压 | VISO | 3.13 | 3.3 | 3.47 | V | IISO = 0 到 75mA，VCC = 3.3V，SEL = GNDB | 10 |
| 最大负载可用电流 | IISO | 130 | mA | A、B 之间 RL = NC，VCC = 5V，SEL = GNDB 或 VISO | 10 | ||
| 最大负载可用电流 | IISO | 75 | mA | A、B 之间 RL = NC，VCC = 3.3V，SEL = GNDB | 10 | ||
| 最大负载可用电流 | IISO | 80 | mA | A、B 之间 RL = 100Ω，VCC = 5V，SEL = VISO | 10 | ||
| 最大负载可用电流 | IISO | 105 | mA | A、B 之间 RL = 100Ω，VCC = 5V，SEL = GNDB | 10 | ||
| 最大负载可用电流 | IISO | 40 | mA | A、B 之间 RL = 100Ω，VCC = 3.3V，SEL = GNDB | 10 | ||
| 最大负载可用电流 | IISO | 55 | mA | A、B 之间 RL = 54Ω，VCC = 5V，SEL = VISO | 10 | ||
| 最大负载可用电流 | IISO | 85 | mA | A、B 之间 RL = 54Ω，VCC = 5V，SEL = GNDB | 10 | ||
| 最大负载可用电流 | IISO | 30 | mA | A、B 之间 RL = 54Ω，VCC = 3.3V，SEL = GNDB | 10 | ||
| 直流线性调整率 | VISO(LINE) | 2 | mV/V | IISO = 50mA，VCC = 4.5 到 5.5V，SEL = GNDB 或 VISO | 10 | ||
| 直流负载调整率 | VISO(LOAD) | 1 | % | IISO = 0 到 130mA，VCC = 5V，SEL = GNDB 或 VISO | 10 | ||
| 逻辑侧供电电流 | ICC | 17 | 28 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间空载，VCC = 3.3V，SEL = GNDB | 10 | |
| 逻辑侧供电电流 | ICC | 15 | 22 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间空载，VCC = 5.0V，SEL = GNDB | 10 | |
| 逻辑侧供电电流 | ICC | 18 | 28 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间空载，VCC = 5.0V，SEL = VISO | 10 | |
| 逻辑侧供电电流 | ICC | 94 | 125 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间 RL = 54Ω，VCC = 3.3V，SEL = GNDB | 10 | |
| 逻辑侧供电电流 | ICC | 82 | 120 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间 RL = 54Ω，VCC = 5.0V，SEL = GNDB | 10 | |
| 逻辑侧供电电流 | ICC | 140 | 200 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间 RL = 54Ω，VCC = 5.0V，SEL = VISO | 10 | |
| 逻辑侧供电电流 | ICC | 65 | 95 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间 RL = 100Ω，VCC = 3.3V，SEL = GNDB | 10 | |
| 逻辑侧供电电流 | ICC | 55 | 80 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间 RL = 100Ω，VCC = 5.0V，SEL = GNDB | 10 | |
| 逻辑侧供电电流 | ICC | 93 | 135 | mA | DE = VCC，RE = 0V，DI = 0V；A、B 之间 RL = 100Ω，VCC = 5.0V，SEL = VISO | 10 | |
| 热阻 RθJA（IC 结至环境） | RθJA | 68.5 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
CA-IS3092VW - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is3092vw-etched.step/ca-is3092vw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3092vw.step/ca-is3092vw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (30 pp, sha256
3f183d2ed5354b3d, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).