CA-IS3050G

{
  "schema_version": 1,
  "type": "component",
  "slug": "ca-is3050g",
  "title": "CA-IS3050G",
  "brief": "Chipanalog CAN Controllers, SOIC-8-300mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "interface",
    "ca-is3050g"
  ],
  "component": {
    "mpn": "CA-IS3050G",
    "manufacturer": "Chipanalog",
    "package": "SOIC-8-300mil",
    "pin_count": 8,
    "category": "Interface",
    "subcategory": "CAN Controllers",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/832346a72be9b41406a7fac96cd44f37.pdf",
    "parts": {
      "symbol": "ca-is3050g.kicad_sym",
      "footprint": "ca-is3050g.kicad_mod",
      "model_3d": "ca-is3050g-etched.glb",
      "model_3d_plain": "ca-is3050g.glb",
      "model_3d_step": "ca-is3050g-etched.step",
      "model_3d_step_plain": "ca-is3050g.step",
      "lbr": "ca-is3050g.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "VCC1",
        "type": "power_in",
        "description": "Power supply input for the logic side (2.5-5.5 V). Bypass VCC1 to GND1 with a 0.1 µF capacitor as close to the device as possible."
      },
      {
        "number": "2",
        "name": "RXD",
        "type": "output",
        "description": "Receiver output (logic side, digital). RXD is high when the bus is in the recessive state and low when the bus is in the dominant state. Output current is ±4 mA."
      },
      {
        "number": "3",
        "name": "TXD",
        "type": "input",
        "description": "Driver data input (logic side, digital). When TXD is low, CANH/CANL are driven to the dominant state; when TXD is high, the driver is off and the bus is left in the recessive state."
      },
      {
        "number": "4",
        "name": "GND1",
        "type": "power_in",
        "description": "Logic-side ground reference for VCC1, TXD, and RXD."
      },
      {
        "number": "5",
        "name": "GND2",
        "type": "power_in",
        "description": "Bus-side ground reference for VCC2, CANH, and CANL. Isolated from GND1 by the SiO2 isolation barrier."
      },
      {
        "number": "6",
        "name": "CANL",
        "type": "bidirectional",
        "description": "Low-level CAN differential bus line. ±58 V fault tolerant with ±30 V extended common-mode input range."
      },
      {
        "number": "7",
        "name": "CANH",
        "type": "bidirectional",
        "description": "High-level CAN differential bus line. ±58 V fault tolerant with ±30 V extended common-mode input range."
      },
      {
        "number": "8",
        "name": "VCC2",
        "type": "power_in",
        "description": "Power supply input for the bus side (4.5-5.5 V). Bypass VCC2 to GND2 with a 0.1 µF capacitor as close to the device as possible."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/832346a72be9b41406a7fac96cd44f37.pdf",
        "pages": 25,
        "sha256": "202103ff414ec669",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ca-is3050g.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ca-is3050g-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "345bc7f709b7bbe2ed473ed5ce1b5fabdce33a2acf215b816069df88edaf85a8",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Chipanalog",
      "Package": "SOIC-8-300mil",
      "Category": "Interface",
      "Pins": "8"
    }
  },
  "variants": [
    {
      "mpn": "CA-IS3050GG",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3050GW",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3050GU",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IS3050GWG",
      "kind": "packaging"
    }
  ],
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "ca-is3050g"
  ],
  "discovery_pitch": "CA-IS3050G (Chipanalog) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ca-is3050g.kicad_sym",
    "ca-is3050g.kicad_mod",
    "ca-is3050g.glb",
    "ca-is3050g.step",
    "ca-is3050g.lbr",
    "docs/hero.png",
    "docs/ca-is3050g-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T18:24:21.111Z"
}