component
CA-IS3020S
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
CA-IS3020S
Chipanalog · Digital Isolators · SOIC-8
CA-IS3020S from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A power supply, recommended 3 V to 5.5 V, with a 0.1 µF decoupling capacitor to GNDA placed within 2 mm. |
| 2 | SDAA | bidirectional | Side A open-drain bidirectional data I/O with up to 3.5 mA pull-down capability and up to 40 pF load capacitance. |
| 3 | SCLA | bidirectional | Side A open-drain bidirectional clock I/O with up to 3.5 mA pull-down capability and up to 40 pF load capacitance. |
| 4 | GNDA | power_in | Side A ground reference. |
| 5 | GNDB | power_in | Side B ground reference. |
| 6 | SCLB | bidirectional | Side B open-drain bidirectional clock I/O with up to 35 mA pull-down capability and up to 400 pF load capacitance. |
| 7 | SDAB | bidirectional | Side B open-drain bidirectional data I/O with up to 35 mA pull-down capability and up to 400 pF load capacitance. |
| 8 | VDDB | power_in | Side B power supply, recommended 3 V to 5.5 V, with a 0.1 µF decoupling capacitor to GNDB placed within 2 mm. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDDA, VDDB | -0.5 | 6 | V | 5 | ||
| A-side output current | IOA | -20 | 20 | mA | 5 | ||
| B-side output current | IOB | -100 | 100 | mA | 5 | ||
| Junction temperature | TJ | 150 | °C | 5 | |||
| Storage temperature | TSTG | -65 | 150 | °C | 5 | ||
| ESD HBM | VESD | -8000 | 8000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 5 | |
| ESD CDM | VESD | -2000 | 2000 | V | JESD22-C101, all pins | 5 | |
| Supply voltage | VDDA, VDDB | 3 | 5.5 | V | 5 | ||
| A-side input low voltage | VILA | 0 | 0.5 | V | 5 | ||
| A-side output low current | IOLA | 0.5 | 3.5 | mA | 5 | ||
| B-side output low current | IOLB | 0.5 | 35 | mA | 5 | ||
| A-side load capacitance | C1 | 40 | pF | 5 | |||
| B-side load capacitance | C2 | 400 | pF | 5 | |||
| Signal transmission rate | fMAX | 1 | MHz | max bus load capacitance and max pull-down current | 5 | ||
| Ambient temperature | TA | -55 | 125 | °C | 5 | ||
| Junction temperature | TJ | -55 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 109 | °C/W | S (SOIC) 8 pins | 6 | ||
| Maximum power dissipation | PD | 86 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, C1 = 40pF, C2 = 400pF, 1MHz 50% duty square wave | 6 | ||
| A-side low-level input threshold | VILTA | 450 | 500 | 550 | mV | SDAA and SCLA | 8 |
| A-side high-level input threshold | VIHTA | 500 | 600 | 700 | mV | SDAA and SCLA | 8 |
| A-side low-level output voltage | VOLA | 650 | 800 | mV | 0.5mA≤(ISDAA and ISCLA)≤3.5mA | 8 | |
| Output low voltage and high input threshold difference | ΔVOITA | 50 | mV | 0.5mA≤(ISDAA and ISCLA)≤3.5mA | 8 | ||
| B-side low-level input threshold | VILTB | 1 | 1.23 | 1.4 | V | SDAB and SCLB | 8 |
| B-side high-level input threshold | VIHTB | 1.4 | 1.67 | 1.9 | V | SDAB and SCLB | 8 |
| B-side input threshold hysteresis | VHYSB | 0.3 | 0.44 | 0.5 | V | VIHTB - VILTB | 8 |
| B-side low-level output voltage | VOLB | 0.4 | V | 0.5mA≤(ISDAA and ISCLA)≤35mA | 8 | ||
| Input leakage current | /IL/ | 1 | μA | VSDAA = VSCLA = VDDA, VSDAB = VSCLB = VDDB | 8 | ||
| Input capacitance to ground | CI | 3 | pF | 8 | |||
| Common-mode transient immunity | CMTI | 100 | 150 | kV/μs | see Figure 7-3 | 8 | |
| Undervoltage threshold | VDDUV | 1.95 | 2.24 | 2.375 | V | 8 | |
| IDDA, inputs low | IDDA | 3.4 | 5.1 | mA | 3 V ≤ VDDA, VDDB ≤ 3.6 V; VSDAA = VSCLA = GNDA; VSDAB = VSCLB = GNDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 | |
| IDDB, inputs low | IDDB | 3 | 4.6 | mA | 3 V ≤ VDDA, VDDB ≤ 3.6 V; VSDAA = VSCLA = GNDA; VSDAB = VSCLB = GNDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 | |
| IDDA, inputs high | IDDA | 2.2 | 3.4 | mA | 3 V ≤ VDDA, VDDB ≤ 3.6 V; VSDAA = VSCLA = VDDA; VSDAB = VSCLB = VDDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 | |
| IDDB, inputs high | IDDB | 1.9 | 2.9 | mA | 3 V ≤ VDDA, VDDB ≤ 3.6 V; VSDAA = VSCLA = VDDA; VSDAB = VSCLB = VDDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 | |
| IDDA, inputs low | IDDA | 3.5 | 5.2 | mA | 4.5 V ≤ VDDA, VDDB ≤ 5.5V; VSDAA = VSCLA = GNDA; VSDAB = VSCLB = GNDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 | |
| IDDB, inputs low | IDDB | 3.1 | 4.7 | mA | 4.5 V ≤ VDDA, VDDB ≤ 5.5V; VSDAA = VSCLA = GNDA; VSDAB = VSCLB = GNDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 | |
| IDDA, inputs high | IDDA | 2.3 | 3.5 | mA | 4.5 V ≤ VDDA, VDDB ≤ 5.5V; VSDAA = VSCLA = VDDA; VSDAB = VSCLB = VDDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 | |
| IDDB, inputs high | IDDB | 2 | 3 | mA | 4.5 V ≤ VDDA, VDDB ≤ 5.5V; VSDAA = VSCLA = VDDA; VSDAB = VSCLB = VDDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 | |
| Fall time SDAA/SCLA | tf1 | 4 | 6 | 9 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, C1 = 40pF; 0.7 VDDA to 0.3 VDDA | 10 |
| Fall time SDAA/SCLA | tf1 | 23 | 37 | 56 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, C1 = 40pF; 0.9 VDDA to 900mV | 10 |
| Fall time SDAB/SCLB | tf2 | 1 | 3 | 5 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R2 = 143Ω, C2 = 400pF; 0.7 VDDB to 0.3 VDDB | 10 |
| Fall time SDAB/SCLB | tf2 | 4 | 8 | 16 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R2 = 143Ω, C2 = 400pF; 0.9 VDDB to 400mV | 10 |
| A to B rising propagation delay | tPLHA-B | 94 | 136 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, R2 = 143Ω, C1 = C2 = 10pF; 0.55V to 0.7 VDDB | 10 | |
| A to B falling propagation delay | tPHLA-B | 65 | 121 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, R2 = 143Ω, C1 = C2 = 10pF; 0.7V to 0.4V | 10 | |
| Pulse width distortion A-B | PWDA-B | 29 | 46 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; /tPLHA-B - tPHLA-B/ | 10 | |
| B to A rising propagation delay | tPLHB-A | 57 | 101 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; 0.4 VDDB to 0.7 VDDA | 10 | |
| B to A falling propagation delay | tPHLB-A | 67 | 110 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; 0.4 VDDB to 0.9V | 10 | |
| Pulse width distortion B-A | PWDB-A | 10 | 46 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; /tPLHA-B - tPHLA-B/ | 10 | |
| A-side loop delay | tLOOPA | 166 | 212 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, C1 = 40pF, R2 = 143Ω, C2 = 400pF; 0.4V to 0.3 VDDA | 10 |
CAD (KiCad official)
- Symbol:
CA-IS3020S - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ca-is3020s-etched.step/ca-is3020s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is3020s.step/ca-is3020s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (18 pp, sha256
b933c201dbafbea5, retrieved 2026-10-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CA-IS3020S
**Chipanalog** · Digital Isolators · SOIC-8
CA-IS3020S from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDDA | power_in | Side A power supply, recommended 3 V to 5.5 V, with a 0.1 µF decoupling capacitor to GNDA placed within 2 mm. |
| 2 | SDAA | bidirectional | Side A open-drain bidirectional data I/O with up to 3.5 mA pull-down capability and up to 40 pF load capacitance. |
| 3 | SCLA | bidirectional | Side A open-drain bidirectional clock I/O with up to 3.5 mA pull-down capability and up to 40 pF load capacitance. |
| 4 | GNDA | power_in | Side A ground reference. |
| 5 | GNDB | power_in | Side B ground reference. |
| 6 | SCLB | bidirectional | Side B open-drain bidirectional clock I/O with up to 35 mA pull-down capability and up to 400 pF load capacitance. |
| 7 | SDAB | bidirectional | Side B open-drain bidirectional data I/O with up to 35 mA pull-down capability and up to 400 pF load capacitance. |
| 8 | VDDB | power_in | Side B power supply, recommended 3 V to 5.5 V, with a 0.1 µF decoupling capacitor to GNDB placed within 2 mm. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDDA, VDDB | -0.5 | | 6 | V | | 5 |
| A-side output current | IOA | -20 | | 20 | mA | | 5 |
| B-side output current | IOB | -100 | | 100 | mA | | 5 |
| Junction temperature | TJ | | | 150 | °C | | 5 |
| Storage temperature | TSTG | -65 | | 150 | °C | | 5 |
| ESD HBM | VESD | -8000 | | 8000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 5 |
| ESD CDM | VESD | -2000 | | 2000 | V | JESD22-C101, all pins | 5 |
| Supply voltage | VDDA, VDDB | 3 | | 5.5 | V | | 5 |
| A-side input low voltage | VILA | 0 | | 0.5 | V | | 5 |
| A-side output low current | IOLA | 0.5 | | 3.5 | mA | | 5 |
| B-side output low current | IOLB | 0.5 | | 35 | mA | | 5 |
| A-side load capacitance | C1 | | | 40 | pF | | 5 |
| B-side load capacitance | C2 | | | 400 | pF | | 5 |
| Signal transmission rate | fMAX | | | 1 | MHz | max bus load capacitance and max pull-down current | 5 |
| Ambient temperature | TA | -55 | | 125 | °C | | 5 |
| Junction temperature | TJ | -55 | | 150 | °C | | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 109 | | °C/W | S (SOIC) 8 pins | 6 |
| Maximum power dissipation | PD | | | 86 | mW | VDDA = VDDB = 5.5 V, CL = 15 pF, TJ = 150°C, C1 = 40pF, C2 = 400pF, 1MHz 50% duty square wave | 6 |
| A-side low-level input threshold | VILTA | 450 | 500 | 550 | mV | SDAA and SCLA | 8 |
| A-side high-level input threshold | VIHTA | 500 | 600 | 700 | mV | SDAA and SCLA | 8 |
| A-side low-level output voltage | VOLA | | 650 | 800 | mV | 0.5mA≤(ISDAA and ISCLA)≤3.5mA | 8 |
| Output low voltage and high input threshold difference | ΔVOITA | 50 | | | mV | 0.5mA≤(ISDAA and ISCLA)≤3.5mA | 8 |
| B-side low-level input threshold | VILTB | 1 | 1.23 | 1.4 | V | SDAB and SCLB | 8 |
| B-side high-level input threshold | VIHTB | 1.4 | 1.67 | 1.9 | V | SDAB and SCLB | 8 |
| B-side input threshold hysteresis | VHYSB | 0.3 | 0.44 | 0.5 | V | VIHTB - VILTB | 8 |
| B-side low-level output voltage | VOLB | | | 0.4 | V | 0.5mA≤(ISDAA and ISCLA)≤35mA | 8 |
| Input leakage current | /IL/ | | | 1 | μA | VSDAA = VSCLA = VDDA, VSDAB = VSCLB = VDDB | 8 |
| Input capacitance to ground | CI | | 3 | | pF | | 8 |
| Common-mode transient immunity | CMTI | 100 | 150 | | kV/μs | see Figure 7-3 | 8 |
| Undervoltage threshold | VDDUV | 1.95 | 2.24 | 2.375 | V | | 8 |
| IDDA, inputs low | IDDA | | 3.4 | 5.1 | mA | 3 V ≤ VDDA, VDDB ≤ 3.6 V; VSDAA = VSCLA = GNDA; VSDAB = VSCLB = GNDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 |
| IDDB, inputs low | IDDB | | 3 | 4.6 | mA | 3 V ≤ VDDA, VDDB ≤ 3.6 V; VSDAA = VSCLA = GNDA; VSDAB = VSCLB = GNDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 |
| IDDA, inputs high | IDDA | | 2.2 | 3.4 | mA | 3 V ≤ VDDA, VDDB ≤ 3.6 V; VSDAA = VSCLA = VDDA; VSDAB = VSCLB = VDDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 |
| IDDB, inputs high | IDDB | | 1.9 | 2.9 | mA | 3 V ≤ VDDA, VDDB ≤ 3.6 V; VSDAA = VSCLA = VDDA; VSDAB = VSCLB = VDDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 |
| IDDA, inputs low | IDDA | | 3.5 | 5.2 | mA | 4.5 V ≤ VDDA, VDDB ≤ 5.5V; VSDAA = VSCLA = GNDA; VSDAB = VSCLB = GNDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 |
| IDDB, inputs low | IDDB | | 3.1 | 4.7 | mA | 4.5 V ≤ VDDA, VDDB ≤ 5.5V; VSDAA = VSCLA = GNDA; VSDAB = VSCLB = GNDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 |
| IDDA, inputs high | IDDA | | 2.3 | 3.5 | mA | 4.5 V ≤ VDDA, VDDB ≤ 5.5V; VSDAA = VSCLA = VDDA; VSDAB = VSCLB = VDDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 |
| IDDB, inputs high | IDDB | | 2 | 3 | mA | 4.5 V ≤ VDDA, VDDB ≤ 5.5V; VSDAA = VSCLA = VDDA; VSDAB = VSCLB = VDDB; R1 = R2 = OPEN; C1 = C2 = OPEN | 9 |
| Fall time SDAA/SCLA | tf1 | 4 | 6 | 9 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, C1 = 40pF; 0.7 VDDA to 0.3 VDDA | 10 |
| Fall time SDAA/SCLA | tf1 | 23 | 37 | 56 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, C1 = 40pF; 0.9 VDDA to 900mV | 10 |
| Fall time SDAB/SCLB | tf2 | 1 | 3 | 5 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R2 = 143Ω, C2 = 400pF; 0.7 VDDB to 0.3 VDDB | 10 |
| Fall time SDAB/SCLB | tf2 | 4 | 8 | 16 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R2 = 143Ω, C2 = 400pF; 0.9 VDDB to 400mV | 10 |
| A to B rising propagation delay | tPLHA-B | | 94 | 136 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, R2 = 143Ω, C1 = C2 = 10pF; 0.55V to 0.7 VDDB | 10 |
| A to B falling propagation delay | tPHLA-B | | 65 | 121 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, R2 = 143Ω, C1 = C2 = 10pF; 0.7V to 0.4V | 10 |
| Pulse width distortion A-B | PWDA-B | | 29 | 46 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; /tPLHA-B - tPHLA-B/ | 10 |
| B to A rising propagation delay | tPLHB-A | | 57 | 101 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; 0.4 VDDB to 0.7 VDDA | 10 |
| B to A falling propagation delay | tPHLB-A | | 67 | 110 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; 0.4 VDDB to 0.9V | 10 |
| Pulse width distortion B-A | PWDB-A | | 10 | 46 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; /tPLHA-B - tPHLA-B/ | 10 |
| A-side loop delay | tLOOPA | | 166 | 212 | ns | 4.5 V ≤ VDDA, VDDB ≤ 5.5 V; R1 = 1430Ω, C1 = 40pF, R2 = 143Ω, C2 = 400pF; 0.4V to 0.3 VDDA | 10 |
## CAD (KiCad official)
- Symbol: `CA-IS3020S`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ca-is3020s-etched.step` / `ca-is3020s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is3020s.step` / `ca-is3020s.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Chipanalog datasheet](docs/ca-is3020s-datasheet.pdf) (18 pp, sha256 `b933c201dbafbea5`, retrieved 2026-10-26, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ca-is3020s-datasheet.pdf)