# CA-IS2092W

**Chipanalog** · RS-485/RS-422 ICs · SOIC-16-300mil

CA-IS2092W from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Side A supply voltage, 3 V to 5.5 V recommended (3.3 V typ), and it must satisfy VCC ≥ VISO. |
| 2 | GNDA | power_in | Side A ground reference. |
| 3 | RO | output | Receiver output. |
| 4 | RE | input | Receiver enable, active low; when RE is high the receiver output is high impedance. |
| 5 | DE | input | Driver enable, active high; when DE is low the driver outputs are high impedance, and DE low with RE low puts the device in receive mode. |
| 6 | DI | input | Driver data input; DI high gives a high level on the non-inverting bus output and a low level on the inverting output, and DI low gives the opposite. |
| 7 | GNDA | power_in | Side A ground reference. |
| 8 | GNDA | power_in | Side A ground reference. |
| 9 | GNDB | power_in | Side B (bus side) ground reference. |
| 10 | SEL | input | VISO output voltage select: tied to VISO gives 5 V, tied to GNDB or floating gives 3.3 V, and with VCC = 3.3 V it may only be grounded or floating. |
| 11 | NC | unconnected | No internal connection. |
| 12 | A | bidirectional | Bus non-inverting (positive) receiver input and driver output. |
| 13 | B | bidirectional | Bus inverting (negative) receiver input and driver output. |
| 14 | NC | unconnected | No internal connection. |
| 15 | GNDB | power_in | Side B (bus side) ground reference. |
| 16 | VISO | power_out | Side B isolated supply output, 3.3 V or 5.0 V selected by SEL. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC, VISO | VCC, VISO | -0.5 |  | 6 | V |  | 5 |
| Input voltage | Vin | -0.5 |  |  | V | max VCC+0.5, not to exceed 6 V | 5 |
| Output current | IO | -20 |  | 20 | mA |  | 5 |
| Junction temperature | TJ |  |  | 150 | °C |  | 5 |
| Storage temperature | TSTG | -65 |  | 150 | °C |  | 5 |
| ESD HBM, bus pins to GNDB | VESD | -6000 |  | 6000 | V | ANSI/ESDA/JEDEC JS-001, bus pins to GNDB | 5 |
| ESD HBM, all pins | VESD | -6000 |  | 6000 | V | ANSI/ESDA/JEDEC JS-001, all pins | 5 |
| ESD IEC 61000-4-2 contact, bus pins to GNDB | VESD | -8000 |  | 8000 | V | IEC 61000-4-2 contact discharge | 5 |
| ESD IEC 61000-4-2 air, bus pins to GNDB | VESD | -16000 |  | 16000 | V | IEC 61000-4-2 air discharge | 5 |
| ESD CDM, all pins | VESD | -2000 |  | 2000 | V | JEDEC JESD22-C101 | 5 |
| Supply voltage | VCC | 3 | 3.3 | 5.5 | V | VCC ≥ VISO | 5 |
| Bus pin voltage A, B | VOC | -7 |  | 12 | V |  | 5 |
| Differential input voltage A, B | VID | -12 |  | 12 | V |  | 5 |
| Input logic high threshold | VIH | 2 |  |  | V |  | 5 |
| Input logic low threshold | VIL |  |  | 0.8 | V |  | 5 |
| Signaling rate | DR |  |  | 0.5 | Mbps |  | 5 |
| Ambient temperature | TA | -40 | 25 | 125 | °C |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 83.4 |  | °C/W |  | 6 |
| Differential output voltage (no load) | /VOD1/ | 3.3 |  |  | V | IO=0mA, no load, SEL low or floating | 8 |
| Differential output voltage (no load) | /VOD1/ | 4.5 | 5 |  | V | IO=0mA, no load, SEL high | 8 |
| Differential output voltage (loaded) | /VOD2/ | 1.4 |  |  | V | RL=54Ω Fig 10-1, SEL low or floating | 8 |
| Differential output voltage (loaded) | /VOD2/ | 2.5 |  |  | V | RL=54Ω Fig 10-1, SEL high | 8 |
| Differential output voltage (common-mode load) | /VOD3/ | 1 | 1.4 |  | V | Vtest from -7V to 12V, Fig 10-2 | 8 |
| Differential output voltage change | ∆/VOD/ | -0.2 |  | 0.2 | V | RL=54Ω or RL=100Ω Fig 10-1 | 8 |
| Steady-state common-mode output voltage | VOC | 1 |  | 3 | V | RL=54Ω or RL=100Ω Fig 10-1 | 8 |
| Common-mode output voltage change | ∆VOC |  |  | 0.2 | V | RL=54Ω or RL=100Ω Fig 10-1 | 8 |
| Input leakage current | IIL | -20 |  | 20 | µA | DI, DE, RE=0 OR 1 | 8 |
| High-impedance output leakage (A,B) | IOZ |  | 60 | 100 | µA | DE=0, RE=0, VCC=0 or 5V, VIN=12V | 8 |
| High-impedance output leakage (A,B) | IOZ | -100 | -60 |  | µA | DE=0, RE=0, VCC=0 or 5V, VIN=-7V | 8 |
| Driver short-circuit current (VO=HIGH) | Ios1 |  |  | 44 | mA | DE=RE=1, DI=1, VA=-7V, VB=12V | 8 |
| Driver short-circuit current (VO=LOW) | Ios2 |  |  | 44 | mA | DE=RE=1, DI=0, VA=-7V, VB=12V | 8 |
| Common-mode transient immunity | CMTI |  | 150 |  | kV/µS | VCM=1200V; Fig 10-9 | 8 |
| Receiver output high voltage | VOH |  | 4.8 |  | V | VCC=5V, IOH=4mA; min VCC-0.4 | 9 |
| Receiver output low voltage | VOL |  | 0.2 | 0.4 | V | VCC=5V, IOL=4mA | 9 |
| Positive input threshold | VIT+(IN) | -100 |  | -20 | mV |  | 9 |
| Negative input threshold | VIT-(IN) | -200 |  | -130 | mV |  | 9 |
| Input threshold hysteresis | VI(HYS) |  | 30 |  | mV |  | 9 |
| Bus input current | II |  | 0.04 | 0.1 | mA | VA or VB=12V, other input 0V | 9 |
| Bus input current, power off | II |  | 0.06 | 0.13 | mA | VA or VB=12V, power off, other input 0V | 9 |
| Bus input current | II | -0.1 | -0.04 |  | mA | VA or VB=-7V, other input 0V | 9 |
| Differential input resistance | RID |  | 450 |  | KΩ | A, B, -7V<VCM<12V | 9 |
| Isolated output voltage | VISO |  | 3.3 |  | V | VCC=5V, no load between A and B, SEL=0 or floating | 9 |
| Isolated output voltage | VISO |  | 5 |  | V | VCC=5V, no load between A and B, SEL=1 | 9 |
| Logic-side supply current | ICC |  |  | 69 | mA | 54Ω load between A and B, VCC=3.3V, /RE=0, DE=1, DI=0, SEL=0 | 9 |
| Logic-side supply current | ICC |  |  | 96 | mA | 54Ω load between A and B, VCC=5V, /RE=0, DE=1, DI=0, SEL=1 | 9 |
| Driver propagation delay | tPLH, tPHL | 1 |  | 1.5 | us | Fig 10-3, 10-4, 10-8 | 9 |
| Driver pulse width distortion | PWD |  |  | 100 | ns | /tPLH-tPHL/ | 9 |
| Driver output rise time | tr |  |  | 100 | ns | Rdiff=54Ω, CL1=CL2=50pF | 10 |
| Driver output fall time | tf |  |  | 100 | ns | Rdiff=54Ω, CL1=CL2=50pF | 10 |
| Driver enable propagation delay | tPZH/tPZL |  |  | 500 | ns |  | 10 |
| Driver disable propagation delay | tPHZ/tPLZ |  |  | 500 | ns |  | 10 |
| Receiver propagation delay | tPLH, tPHL | 1 |  | 1.5 | us | Fig 10-5, 10-6, 10-7; Rdiff=54Ω, CL1=CL2=50pF | 10 |
| Receiver pulse width distortion | PWD |  |  | 100 | ns | /tPLH-tPHL/ | 10 |
| Receiver output rise time | tr |  |  | 100 | ns |  | 10 |
| Receiver output fall time | tf |  |  | 100 | ns |  | 10 |
| Receiver disable time | tPHZ, tPLZ |  |  | 200 | ns |  | 10 |
| Receiver enable time | tPZH, tPZL |  |  | 200 | ns |  | 10 |

## CAD (KiCad official)

- Symbol: `CA-IS2092W`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `ca-is2092w-etched.step` / `ca-is2092w-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is2092w.step` / `ca-is2092w.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Chipanalog datasheet](docs/ca-is2092w-datasheet.pdf) (21 pp, sha256 `6bfc12f6fb98d7db`, retrieved 2026-10-22, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ca-is2092w-datasheet.pdf)