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CA-IS1306AM25W
Public Made by Adomby adom
Chipanalog Digital Isolators, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CA-IS1306AM25W
Chipanalog · Digital Isolators · SOIC-16-300mil
CA-IS1306AM25W from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVDD | power_in | Power supply input for the input-side (analog input-side), 3.0V to 5.5V; bypass AVDD to AGND with 0.1μF//2.2μF capacitors as close to the device as possible. |
| 2 | AINP | input | Noninverting analog input; external shunt resistor connection input (power-side) for current sense. |
| 3 | AINN | input | Inverting analog input; external shunt resistor connection input (load-side) for current sense. |
| 4 | AGND | power_in | High-side (input-side) ground. |
| 5 | NC | unconnected | No connection; left floating or connect to AVDD or AGND. |
| 6 | NC | unconnected | No connection; left floating or connect to AVDD or AGND. |
| 7 | NC | unconnected | No connection; left floating or connect to AVDD or AGND. |
| 8 | AGND | power_in | High-side (input-side) ground. |
| 9 | DGND | power_in | Low-side (output-side) ground. |
| 10 | NC | unconnected | No connection; left floating or connect to DVDD or DGND. |
| 11 | DOUT | output | Modulator bit-stream output. |
| 12 | NC | unconnected | No connection; left floating or connect to DVDD or DGND. |
| 13 | CLKIN | input | Modulator clock input (5 MHz to 21 MHz) with internal 1.5-MΩ pulldown resistor. |
| 14 | DVDD | power_in | Low-side (digital output-side) power supply, 3.0V to 5.5V; bypass DVDD to DGND with 0.1μF//2.2μF capacitors as close to the device as possible. |
| 15 | NC | unconnected | No connection; left floating or connect to DVDD or DGND. |
| 16 | DGND | power_in | Low-side (output-side) ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (AVDD, DVDD) | AVDD, DVDD | -0.5 | 6.5 | V | 7 | ||
| Analog input voltage (AINP, AINN) | -6 | 6.5 | V | AGND, 6 to 6.5 V | 7 | ||
| Digital input or output voltage (CLKIN, DOUT) | -0.5 | 0.5 | V | DGND, 0.5 to DVDD + 0.5 | 7 | ||
| Input current to any pin except supply pins | IIN | -10 | 10 | mA | 7 | ||
| Junction temperature | TJ | 150 | °C | 7 | |||
| Storage temperature | TSTG | -65 | 150 | °C | 7 | ||
| High-side supply voltage | AVDD | 3 | 5 | 5.5 | V | with respect to AGND | 7 |
| Low-side supply voltage | DVDD | 3 | 3.3 | 5.5 | V | with respect to DGND | 7 |
| Operating ambient temperature | TA | -40 | 125 | °C | 7 | ||
| Differential analog input range | AINP, AINN | -250 | 250 | mV | 7 | ||
| Junction-to-ambient thermal resistance | RθJA | 110.1 | °C/W | 7 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 51.7 | °C/W | 7 | |||
| Junction-to-board thermal resistance | RθJB | 66.4 | °C/W | 7 | |||
| Specified linear full-scale input range | VFSR | -250 | 250 | mV | AINP, AINN | 10 | |
| Operating common-mode input voltage | VCM | -0.16 | V | (AINP + AINN) / 2 to AGND; max AVDD, 2.1 | 10 | ||
| Input current | IIN | -41 | -30 | -24 | μA | AINP = AINN = AGND, IIN = (IINP + IINN) / 2 | 10 |
| Common-mode transient immunity | CMTI | 100 | 150 | kV/μs | /AGND, DGND/ = 1.5 kV | 10 | |
| Differential nonlinearity | DNL | -0.99 | 0.99 | LSB | Resolution: 16 bits | 10 | |
| Integral nonlinearity | INL | -6 | 2 | 6 | LSB | Resolution: 16 bits | 10 |
| Offset error | EO | -100 | 4.5 | 100 | μV | Initial, at TA = 25°C, AINP = AINN = AGND | 10 |
| Offset drift | TCEO | -3.5 | 0.5 | 3.5 | μV/°C | 10 | |
| Gain error | EG | -0.2 | 0.05 | 0.2 | % | Initial, at TA = 25°C | 10 |
| Gain drift | TCEG | -40 | 20 | 40 | ppm/°C | 10 | |
| Digital input current | IIN | 0 | 7 | μA | DGND ≤ VIN ≤ DVDD | 11 | |
| Logic high-level input voltage | VIH | 0.7 | V | min 0.7 × DVDD; max DVDD + 0.3 V; min value is the 0.7 factor times DVDD | 11 | ||
| Logic low-level input voltage | VIL | -0.3 | 0.3 | V | max 0.3 × DVDD | 11 | |
| Logic high-level output voltage | VOH | -0.1 | V | IOH = -20 μA; min DVDD, 0.1 | 11 | ||
| Logic high-level output voltage | VOH | -0.4 | V | IOH = -4 mA; min DVDD, 0.4 | 11 | ||
| Logic low-level output voltage | VOL | 0.1 | V | IOL = 20 μA | 11 | ||
| Logic low-level output voltage | VOL | 0.4 | V | IOL = 4 mA | 11 | ||
| AVDD undervoltage threshold | AVDDUV | 2.5 | 2.7 | V | AVDD rising | 11 | |
| High-side supply current | IAVDD | 10.5 | 15 | mA | 3.0 V ≤ AVDD ≤ 3.6 V | 11 | |
| High-side supply current | IAVDD | 11.5 | 16.5 | mA | 4.5 V ≤ AVDD ≤ 5.5 V | 11 | |
| Low-side supply current | IDVDD | 3.3 | 5.3 | mA | 3.0 V ≤ DVDD ≤ 3.6 V, CL = 15 pF | 11 | |
| Low-side supply current | IDVDD | 4 | 7 | mA | 4.5 V ≤ DVDD ≤ 5.5 V, CL = 15 pF | 11 | |
| CLKIN clock frequency | fCLKIN | 5 | 21 | MHz | 4.5 V ≤ AVDD ≤ 5.5 V | 12 | |
| CLKIN clock frequency | fCLKIN | 5 | 20 | MHz | 3.0 V ≤ AVDD ≤ 5.5 V | 12 | |
| CLKIN clock duty cycle | Duty Cycle | 45 | 50 | 55 | % | tHIGH / tCLKIN, 3.0 V ≤ AVDD ≤ 5.5 V | 12 |
| CLKIN clock duty cycle | Duty Cycle | 42.5 | 50 | 57.5 | % | tHIGH / tCLKIN, 4.5 V ≤ AVDD ≤ 5.5 V | 12 |
| Delay time of DOUT after rising edge of CLKIN | td | 16 | ns | CL = 15 pF | 12 | ||
| Rise time of DOUT | tr | 1.8 | 5 | ns | CL = 15 pF | 12 | |
| Fall time of DOUT | tf | 1.8 | 5 | ns | CL = 15 pF | 12 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | the AINN pins to large copper traces. Keep the part away from other heat‐generating devices. For accurate measurement of | 25 |
CAD (KiCad official)
- Symbol:
CA-IS1306AM25W - Footprint:
Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is1306am25w-etched.step/ca-is1306am25w-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is1306am25w.step/ca-is1306am25w.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (29 pp, sha256
301d239d82f9aa4d, retrieved 2026-11-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CA-IS1306AM25W
**Chipanalog** · Digital Isolators · SOIC-16-300mil
CA-IS1306AM25W from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVDD | power_in | Power supply input for the input-side (analog input-side), 3.0V to 5.5V; bypass AVDD to AGND with 0.1μF//2.2μF capacitors as close to the device as possible. |
| 2 | AINP | input | Noninverting analog input; external shunt resistor connection input (power-side) for current sense. |
| 3 | AINN | input | Inverting analog input; external shunt resistor connection input (load-side) for current sense. |
| 4 | AGND | power_in | High-side (input-side) ground. |
| 5 | NC | unconnected | No connection; left floating or connect to AVDD or AGND. |
| 6 | NC | unconnected | No connection; left floating or connect to AVDD or AGND. |
| 7 | NC | unconnected | No connection; left floating or connect to AVDD or AGND. |
| 8 | AGND | power_in | High-side (input-side) ground. |
| 9 | DGND | power_in | Low-side (output-side) ground. |
| 10 | NC | unconnected | No connection; left floating or connect to DVDD or DGND. |
| 11 | DOUT | output | Modulator bit-stream output. |
| 12 | NC | unconnected | No connection; left floating or connect to DVDD or DGND. |
| 13 | CLKIN | input | Modulator clock input (5 MHz to 21 MHz) with internal 1.5-MΩ pulldown resistor. |
| 14 | DVDD | power_in | Low-side (digital output-side) power supply, 3.0V to 5.5V; bypass DVDD to DGND with 0.1μF//2.2μF capacitors as close to the device as possible. |
| 15 | NC | unconnected | No connection; left floating or connect to DVDD or DGND. |
| 16 | DGND | power_in | Low-side (output-side) ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (AVDD, DVDD) | AVDD, DVDD | -0.5 | | 6.5 | V | | 7 |
| Analog input voltage (AINP, AINN) | | -6 | | 6.5 | V | AGND, 6 to 6.5 V | 7 |
| Digital input or output voltage (CLKIN, DOUT) | | -0.5 | | 0.5 | V | DGND, 0.5 to DVDD + 0.5 | 7 |
| Input current to any pin except supply pins | IIN | -10 | | 10 | mA | | 7 |
| Junction temperature | TJ | | | 150 | °C | | 7 |
| Storage temperature | TSTG | -65 | | 150 | °C | | 7 |
| High-side supply voltage | AVDD | 3 | 5 | 5.5 | V | with respect to AGND | 7 |
| Low-side supply voltage | DVDD | 3 | 3.3 | 5.5 | V | with respect to DGND | 7 |
| Operating ambient temperature | TA | -40 | | 125 | °C | | 7 |
| Differential analog input range | AINP, AINN | -250 | | 250 | mV | | 7 |
| Junction-to-ambient thermal resistance | RθJA | | 110.1 | | °C/W | | 7 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 51.7 | | °C/W | | 7 |
| Junction-to-board thermal resistance | RθJB | | 66.4 | | °C/W | | 7 |
| Specified linear full-scale input range | VFSR | -250 | | 250 | mV | AINP, AINN | 10 |
| Operating common-mode input voltage | VCM | -0.16 | | | V | (AINP + AINN) / 2 to AGND; max AVDD, 2.1 | 10 |
| Input current | IIN | -41 | -30 | -24 | μA | AINP = AINN = AGND, IIN = (IINP + IINN) / 2 | 10 |
| Common-mode transient immunity | CMTI | 100 | 150 | | kV/μs | /AGND, DGND/ = 1.5 kV | 10 |
| Differential nonlinearity | DNL | -0.99 | | 0.99 | LSB | Resolution: 16 bits | 10 |
| Integral nonlinearity | INL | -6 | 2 | 6 | LSB | Resolution: 16 bits | 10 |
| Offset error | EO | -100 | 4.5 | 100 | μV | Initial, at TA = 25°C, AINP = AINN = AGND | 10 |
| Offset drift | TCEO | -3.5 | 0.5 | 3.5 | μV/°C | | 10 |
| Gain error | EG | -0.2 | 0.05 | 0.2 | % | Initial, at TA = 25°C | 10 |
| Gain drift | TCEG | -40 | 20 | 40 | ppm/°C | | 10 |
| Digital input current | IIN | 0 | | 7 | μA | DGND ≤ VIN ≤ DVDD | 11 |
| Logic high-level input voltage | VIH | 0.7 | | | V | min 0.7 × DVDD; max DVDD + 0.3 V; min value is the 0.7 factor times DVDD | 11 |
| Logic low-level input voltage | VIL | -0.3 | | 0.3 | V | max 0.3 × DVDD | 11 |
| Logic high-level output voltage | VOH | -0.1 | | | V | IOH = -20 μA; min DVDD, 0.1 | 11 |
| Logic high-level output voltage | VOH | -0.4 | | | V | IOH = -4 mA; min DVDD, 0.4 | 11 |
| Logic low-level output voltage | VOL | | | 0.1 | V | IOL = 20 μA | 11 |
| Logic low-level output voltage | VOL | | | 0.4 | V | IOL = 4 mA | 11 |
| AVDD undervoltage threshold | AVDDUV | | 2.5 | 2.7 | V | AVDD rising | 11 |
| High-side supply current | IAVDD | | 10.5 | 15 | mA | 3.0 V ≤ AVDD ≤ 3.6 V | 11 |
| High-side supply current | IAVDD | | 11.5 | 16.5 | mA | 4.5 V ≤ AVDD ≤ 5.5 V | 11 |
| Low-side supply current | IDVDD | | 3.3 | 5.3 | mA | 3.0 V ≤ DVDD ≤ 3.6 V, CL = 15 pF | 11 |
| Low-side supply current | IDVDD | | 4 | 7 | mA | 4.5 V ≤ DVDD ≤ 5.5 V, CL = 15 pF | 11 |
| CLKIN clock frequency | fCLKIN | 5 | | 21 | MHz | 4.5 V ≤ AVDD ≤ 5.5 V | 12 |
| CLKIN clock frequency | fCLKIN | 5 | | 20 | MHz | 3.0 V ≤ AVDD ≤ 5.5 V | 12 |
| CLKIN clock duty cycle | Duty Cycle | 45 | 50 | 55 | % | tHIGH / tCLKIN, 3.0 V ≤ AVDD ≤ 5.5 V | 12 |
| CLKIN clock duty cycle | Duty Cycle | 42.5 | 50 | 57.5 | % | tHIGH / tCLKIN, 4.5 V ≤ AVDD ≤ 5.5 V | 12 |
| Delay time of DOUT after rising edge of CLKIN | td | | | 16 | ns | CL = 15 pF | 12 |
| Rise time of DOUT | tr | | 1.8 | 5 | ns | CL = 15 pF | 12 |
| Fall time of DOUT | tf | | 1.8 | 5 | ns | CL = 15 pF | 12 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | the AINN pins to large copper traces. Keep the part away from other heat‐generating devices. For accurate measurement of | 25 |
## CAD (KiCad official)
- Symbol: `CA-IS1306AM25W`
- Footprint: `Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `ca-is1306am25w-etched.step` / `ca-is1306am25w-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is1306am25w.step` / `ca-is1306am25w.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Chipanalog datasheet](docs/ca-is1306am25w-datasheet.pdf) (29 pp, sha256 `301d239d82f9aa4d`, retrieved 2026-11-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ca-is1306am25w-datasheet.pdf)