component
CA-IS1305M25W
Public Made by Adomby adom
Chipanalog Isolated ADCs, SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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c068127
CA-IS1305M25W
Chipanalog · Isolated ADCs · SOIC-16-300mil
CA-IS1305M25W from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connection, but connected to AVDD internally; leave it open or connect to AVDD. |
| 2 | AINP | input | Noninverting analog input; external shunt resistor connection (power-side) for current sense, ±250 mV differential range. |
| 3 | AINN | input | Inverting analog input; external shunt resistor connection (load-side) for current sense. |
| 4 | AGND | power_in | High-side (input-side) ground. |
| 5 | NC | unconnected | No connection; leave open or connect to AVDD or AGND. |
| 6 | NC | unconnected | No connection; leave open or connect to AVDD or AGND. |
| 7 | AVDD | power_in | High-side (analog input-side) power supply input, 4.5 V to 5.5 V. |
| 8 | AGND | power_in | High-side (input-side) ground. |
| 9 | DGND | power_in | Low-side (output-side) ground. |
| 10 | NC | unconnected | No connection; leave open or connect to DVDD or DGND. |
| 11 | DOUT | output | Modulator bit-stream output. |
| 12 | NC | unconnected | No connection; leave open or connect to DVDD or DGND. |
| 13 | CLKIN | input | Modulator clock input, 5 MHz to 21 MHz, with internal 1.5-MΩ pulldown resistor. |
| 14 | DVDD | power_in | Low-side (digital output-side) power supply, 3.0 V to 5.5 V; bypass to DGND. |
| 15 | NC | unconnected | No connection; leave open or connect to DVDD or DGND. |
| 16 | DGND | power_in | Low-side (output-side) ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Isolators |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Specified linear full-scale input range | VFSR | -250 | 250 | mV | AINP, AINN | 9 | |
| Operating common-mode input voltage | VCM | -0.16 | V | (AINP + AINN) / 2 to AGND; max is AVDD, 2.1 | 9 | ||
| Input current | IIN | -41 | -30 | -24 | μA | AINP = AINN = AGND, IIN = (IINP + IINN) / 2 | 9 |
| Common-mode transient immunity | CMTI | 100 | 150 | kV/μs | /AGND, DGND/ = 1.5 kV | 9 | |
| Differential nonlinearity | DNL | -0.99 | 0.99 | LSB | Resolution: 16 bits | 9 | |
| Integral nonlinearity | INL | -6 | 2 | 6 | LSB | Resolution: 16 bits | 9 |
| Offset error | EO | -150 | 4.5 | 150 | μV | Initial, at TA = 25°C, AINP = AINN = AGND | 9 |
| Offset drift | TCEO | -3.5 | 0.5 | 3.5 | μV/°C | 9 | |
| Gain error | EG | -0.3 | 0.05 | 0.3 | % | Initial, at TA = 25°C | 9 |
| Gain drift | TCEG | -40 | 20 | 40 | ppm/°C | 9 | |
| Digital input current | IIN | 0 | 7 | μA | 2.7 V ≤ VIN ≤ 5.5 V | 10 | |
| Logic high-level input voltage | VIH | 0.7 | V | min is 0.7 × DVDD; max is DVDD + 0.3 | 10 | ||
| Logic low-level input voltage | VIL | -0.3 | 0.3 | V | max is 0.3 × DVDD | 10 | |
| Logic high-level output voltage | VOH | 0.1 | V | IOH = -20 μA; printed as DVDD, 0.1 | 10 | ||
| Logic high-level output voltage | VOH | 0.4 | V | IOH = -4 mA; printed as DVDD, 0.4 | 10 | ||
| Logic low-level output voltage | VOL | 0.1 | V | IOL = 20 μA | 10 | ||
| Logic low-level output voltage | VOL | 0.4 | V | IOL = 4 mA | 10 | ||
| AVDD undervoltage threshold | AVDDUV | 2.5 | 2.7 | V | AVDD rising | 10 | |
| High-side supply current | IAVDD | 11.5 | 16.5 | mA | 4.5 V ≤ AVDD ≤ 5.5 V | 10 | |
| Low-side supply current | IDVDD | 3.3 | 5.3 | mA | 3.0 V ≤ DVDD ≤ 3.6 V, CL = 15 pF | 10 | |
| Low-side supply current | IDVDD | 4 | 7 | mA | 4.5 V ≤ DVDD ≤ 5.5 V, CL = 15 pF | 10 | |
| CLKIN clock frequency | fCLKIN | 5 | 21 | MHz | 4.5 V ≤ AVDD ≤ 5.5 V | 11 | |
| CLKIN clock duty cycle | Duty Cycle | 42.5 | 50 | 57.5 | % | tHIGH / tCLKIN, 4.5 V ≤ AVDD ≤ 5.5 V | 11 |
| Hold time of DOUT after rising edge of CLKIN | th | 3.5 | ns | CL = 15 pF | 11 | ||
| Delay time of DOUT after rising edge of CLKIN | td | 16 | ns | CL = 15 pF | 11 | ||
| Rise time of DOUT (10%-90%) | tr | 1.8 | 5 | ns | CL = 15 pF | 11 | |
| Fall time of DOUT (90%-10%) | tf | 1.8 | 5 | ns | CL = 15 pF | 11 | |
| Analog startup time | tastart | 500 | μs | AVDD step to 4.5 V with 3.0 V ≤ DVDD | 11 | ||
| Supply voltage (AVDD, DVDD) | -0.5 | 6.5 | V | 6 | |||
| Analog input voltage (AINP, AINN) | 6.5 | V | min is AGND, 6 | 6 | |||
| Digital input or output voltage (CLKIN, DOUT) | -0.5 | 0.5 | V | DGND, 0.5 to DVDD + 0.5 | 6 | ||
| Input current to any pin except supply pins | IIN | -10 | 10 | mA | 6 | ||
| Junction temperature | TJ | 150 | °C | 6 | |||
| Storage temperature | TSTG | -65 | 150 | °C | 6 | ||
| High-side supply voltage | AVDD | 4.5 | 5 | 5.5 | V | with respect to AGND | 6 |
| Low-side supply voltage | DVDD | 3 | 3.3 | 5.5 | V | with respect to DGND | 6 |
| Operating ambient temperature range | TA | -40 | 125 | °C | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 86.5 | °C/W | 6 | |||
| Maximum power dissipation for both sides | PD | 129.25 | mW | AVDD = DVDD = 5.5 V | 6 | ||
| Maximum power dissipation for high-side | PD1 | 90.75 | mW | AVDD = 5.5 V | 6 | ||
| Maximum power dissipation for low-side | PD2 | 38.5 | mW | DVDD = 5.5 V | 6 | ||
| HBM ESD | VESD | -4000 | 4000 | V | HBM, per ANSI/ESDA/JEDEC JS-001, all pins | 6 | |
| CDM ESD | VESD | -2000 | 2000 | V | CDM, per JEDEC specification JESD22-C101, all pins | 6 | |
| Maximum input voltage before clipping output | VClipping | 320 | mV | AINP, AINN; printed as ±320 | 9 | ||
| Differential input resistance | RIND | 22 | kΩ | 9 | |||
| Input bandwidth | BWIN | 1000 | kHz | -3 dB | 9 | ||
| Signal-to-noise ratio | SNR | 85 | dB | fIN = 1 kHz, BW = 10 kHz | 9 | ||
| Total harmonic distortion | THD | -93 | dB | fIN = 1 kHz, BW = 10 kHz | 9 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pet | Reinforced insulation Maximum repetitive peak isolation | 8 | |
| contacts | copper | sources. To dissipate sense‐resistor heat from large sense currents, solder the AINP and the AINN pins to large copper | 24 |
CAD (KiCad official)
- Symbol:
CA-IS1305M25W - Footprint:
Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm - 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files:
ca-is1305m25w-etched.step/ca-is1305m25w-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-is1305m25w.step/ca-is1305m25w.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (28 pp, sha256
cbeb3da2aa2635aa, retrieved 2026-11-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CA-IS1305M25W
**Chipanalog** · Isolated ADCs · SOIC-16-300mil
CA-IS1305M25W from Chipanalog, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connection, but connected to AVDD internally; leave it open or connect to AVDD. |
| 2 | AINP | input | Noninverting analog input; external shunt resistor connection (power-side) for current sense, ±250 mV differential range. |
| 3 | AINN | input | Inverting analog input; external shunt resistor connection (load-side) for current sense. |
| 4 | AGND | power_in | High-side (input-side) ground. |
| 5 | NC | unconnected | No connection; leave open or connect to AVDD or AGND. |
| 6 | NC | unconnected | No connection; leave open or connect to AVDD or AGND. |
| 7 | AVDD | power_in | High-side (analog input-side) power supply input, 4.5 V to 5.5 V. |
| 8 | AGND | power_in | High-side (input-side) ground. |
| 9 | DGND | power_in | Low-side (output-side) ground. |
| 10 | NC | unconnected | No connection; leave open or connect to DVDD or DGND. |
| 11 | DOUT | output | Modulator bit-stream output. |
| 12 | NC | unconnected | No connection; leave open or connect to DVDD or DGND. |
| 13 | CLKIN | input | Modulator clock input, 5 MHz to 21 MHz, with internal 1.5-MΩ pulldown resistor. |
| 14 | DVDD | power_in | Low-side (digital output-side) power supply, 3.0 V to 5.5 V; bypass to DGND. |
| 15 | NC | unconnected | No connection; leave open or connect to DVDD or DGND. |
| 16 | DGND | power_in | Low-side (output-side) ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-16-300mil |
| Category | Isolators |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Specified linear full-scale input range | VFSR | -250 | | 250 | mV | AINP, AINN | 9 |
| Operating common-mode input voltage | VCM | -0.16 | | | V | (AINP + AINN) / 2 to AGND; max is AVDD, 2.1 | 9 |
| Input current | IIN | -41 | -30 | -24 | μA | AINP = AINN = AGND, IIN = (IINP + IINN) / 2 | 9 |
| Common-mode transient immunity | CMTI | 100 | 150 | | kV/μs | /AGND, DGND/ = 1.5 kV | 9 |
| Differential nonlinearity | DNL | -0.99 | | 0.99 | LSB | Resolution: 16 bits | 9 |
| Integral nonlinearity | INL | -6 | 2 | 6 | LSB | Resolution: 16 bits | 9 |
| Offset error | EO | -150 | 4.5 | 150 | μV | Initial, at TA = 25°C, AINP = AINN = AGND | 9 |
| Offset drift | TCEO | -3.5 | 0.5 | 3.5 | μV/°C | | 9 |
| Gain error | EG | -0.3 | 0.05 | 0.3 | % | Initial, at TA = 25°C | 9 |
| Gain drift | TCEG | -40 | 20 | 40 | ppm/°C | | 9 |
| Digital input current | IIN | 0 | | 7 | μA | 2.7 V ≤ VIN ≤ 5.5 V | 10 |
| Logic high-level input voltage | VIH | 0.7 | | | V | min is 0.7 × DVDD; max is DVDD + 0.3 | 10 |
| Logic low-level input voltage | VIL | -0.3 | | 0.3 | V | max is 0.3 × DVDD | 10 |
| Logic high-level output voltage | VOH | 0.1 | | | V | IOH = -20 μA; printed as DVDD, 0.1 | 10 |
| Logic high-level output voltage | VOH | 0.4 | | | V | IOH = -4 mA; printed as DVDD, 0.4 | 10 |
| Logic low-level output voltage | VOL | | | 0.1 | V | IOL = 20 μA | 10 |
| Logic low-level output voltage | VOL | | | 0.4 | V | IOL = 4 mA | 10 |
| AVDD undervoltage threshold | AVDDUV | | 2.5 | 2.7 | V | AVDD rising | 10 |
| High-side supply current | IAVDD | | 11.5 | 16.5 | mA | 4.5 V ≤ AVDD ≤ 5.5 V | 10 |
| Low-side supply current | IDVDD | | 3.3 | 5.3 | mA | 3.0 V ≤ DVDD ≤ 3.6 V, CL = 15 pF | 10 |
| Low-side supply current | IDVDD | | 4 | 7 | mA | 4.5 V ≤ DVDD ≤ 5.5 V, CL = 15 pF | 10 |
| CLKIN clock frequency | fCLKIN | 5 | | 21 | MHz | 4.5 V ≤ AVDD ≤ 5.5 V | 11 |
| CLKIN clock duty cycle | Duty Cycle | 42.5 | 50 | 57.5 | % | tHIGH / tCLKIN, 4.5 V ≤ AVDD ≤ 5.5 V | 11 |
| Hold time of DOUT after rising edge of CLKIN | th | 3.5 | | | ns | CL = 15 pF | 11 |
| Delay time of DOUT after rising edge of CLKIN | td | | | 16 | ns | CL = 15 pF | 11 |
| Rise time of DOUT (10%-90%) | tr | | 1.8 | 5 | ns | CL = 15 pF | 11 |
| Fall time of DOUT (90%-10%) | tf | | 1.8 | 5 | ns | CL = 15 pF | 11 |
| Analog startup time | tastart | | | 500 | μs | AVDD step to 4.5 V with 3.0 V ≤ DVDD | 11 |
| Supply voltage (AVDD, DVDD) | | -0.5 | | 6.5 | V | | 6 |
| Analog input voltage (AINP, AINN) | | | | 6.5 | V | min is AGND, 6 | 6 |
| Digital input or output voltage (CLKIN, DOUT) | | -0.5 | | 0.5 | V | DGND, 0.5 to DVDD + 0.5 | 6 |
| Input current to any pin except supply pins | IIN | -10 | | 10 | mA | | 6 |
| Junction temperature | TJ | | | 150 | °C | | 6 |
| Storage temperature | TSTG | -65 | | 150 | °C | | 6 |
| High-side supply voltage | AVDD | 4.5 | 5 | 5.5 | V | with respect to AGND | 6 |
| Low-side supply voltage | DVDD | 3 | 3.3 | 5.5 | V | with respect to DGND | 6 |
| Operating ambient temperature range | TA | -40 | | 125 | °C | | 6 |
| Junction-to-ambient thermal resistance | RθJA | | 86.5 | | °C/W | | 6 |
| Maximum power dissipation for both sides | PD | | | 129.25 | mW | AVDD = DVDD = 5.5 V | 6 |
| Maximum power dissipation for high-side | PD1 | | | 90.75 | mW | AVDD = 5.5 V | 6 |
| Maximum power dissipation for low-side | PD2 | | | 38.5 | mW | DVDD = 5.5 V | 6 |
| HBM ESD | VESD | -4000 | | 4000 | V | HBM, per ANSI/ESDA/JEDEC JS-001, all pins | 6 |
| CDM ESD | VESD | -2000 | | 2000 | V | CDM, per JEDEC specification JESD22-C101, all pins | 6 |
| Maximum input voltage before clipping output | VClipping | | 320 | | mV | AINP, AINN; printed as ±320 | 9 |
| Differential input resistance | RIND | | 22 | | kΩ | | 9 |
| Input bandwidth | BWIN | | 1000 | | kHz | -3 dB | 9 |
| Signal-to-noise ratio | SNR | | 85 | | dB | fIN = 1 kHz, BW = 10 kHz | 9 |
| Total harmonic distortion | THD | | -93 | | dB | fIN = 1 kHz, BW = 10 kHz | 9 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pet | | Reinforced insulation Maximum repetitive peak isolation | 8 |
| contacts | copper | | sources. To dissipate sense‐resistor heat from large sense currents, solder the AINP and the AINN pins to large copper | 24 |
## CAD (KiCad official)
- Symbol: `CA-IS1305M25W`
- Footprint: `Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `ca-is1305m25w-etched.step` / `ca-is1305m25w-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-is1305m25w.step` / `ca-is1305m25w.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Chipanalog datasheet](docs/ca-is1305m25w-datasheet.pdf) (28 pp, sha256 `cbeb3da2aa2635aa`, retrieved 2026-11-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ca-is1305m25w-datasheet.pdf)