# CA-IF4905S

**Chipanalog** · RS-485 / RS-422 ICs · SOIC-8

CA-IF4905S from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RO | output | Receiver data output: driven high when VID ≥ -20mV, low when VID ≤ -200mV, and held at fail-safe high on open, short, or idle bus; high-impedance when REB is high or open. |
| 2 | REB | input | Receiver enable, active low with internal pull-up to VCC; REB high or open forces RO to high-impedance. |
| 3 | DE | input | Driver enable, active high with internal pull-down to GND; DE low or open disables the driver and puts A and B in high-impedance. |
| 4 | DI | input | Driver data input with internal pull-up to VCC; when left open with the driver enabled, output A goes high and B goes low. |
| 5 | GND | power_in | Ground reference for the device; all voltages are referenced to GND. |
| 6 | A | bidirectional | Non-inverting receiver input and driver output on the bus; bus pins withstand ±65V fault voltage and operate over a ±40V common-mode range (4.5V to 5.5V VCC), with ±30kV HBM ESD protection. |
| 7 | B | bidirectional | Inverting receiver input and driver output on the bus; bus pins withstand ±65V fault voltage and operate over a ±40V common-mode range (4.5V to 5.5V VCC), with ±30kV HBM ESD protection. |
| 8 | VCC | power_in | Supply input, 3.0V to 5.5V; place at least a 0.1µF bypass capacitor between VCC and GND as close to the pin as possible. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | SOIC-8 |
| Category | Interface |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage (absolute maximum) | VCC | -0.5 |  | 7 | V |  | 5 |
| Bus voltage A, B (absolute maximum) | VIO | -65 |  | 65 | V |  | 5 |
| Junction temperature (absolute maximum) | TJ |  |  | 150 | °C |  | 5 |
| Storage temperature (absolute maximum) | TSTG | -65 |  | 150 | °C |  | 5 |
| VCC supply voltage vs GND (recommended) | VCC | 3 | 5 | 5.5 | V | Referenced to GND | 5 |
| Bus input voltage (recommended) | VIN | -40 |  | 40 | V |  | 5 |
| DI, DE, REB high-level input threshold (recommended) | VIH | 2 |  |  | V | DI, DE, REB pins | 5 |
| DI, DE, REB low-level input threshold (recommended) | VIL | 0 |  | 0.8 | V | DI, DE, REB pins | 5 |
| Differential load resistance | RL | 54 |  |  | Ω |  | 5 |
| Data rate | 1/tUI |  |  | 500 | kbps |  | 5 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 5 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 5 |
| /VOD/ differential output voltage | /VOD/ | 1.2 |  | 2.8 | V | RL = 60Ω, -40V ≤ Vtest ≤ 40V, see Fig 8-1 | 6 |
| /VOD/ differential output voltage | /VOD/ | 2 |  | 2.8 | V | RL = 60Ω, -40V ≤ Vtest ≤ 40V, 4.5V ≤ VCC ≤ 5.5V, see Fig 8-1 | 6 |
| /VOD/ differential output voltage | /VOD/ | 1.7 |  | 3.5 | V | RL = 100Ω, CL = 50pF, see Fig 8-2 | 6 |
| Change in differential output voltage | Δ/VOD/ | -200 |  | 200 | mV | RL = 54Ω or 100Ω, CL = 50pF, see Fig 8-2 | 6 |
| Common-mode output voltage | VOC | 1 |  | 3.2 | V | RL = 54Ω or 100Ω, CL = 50pF, see Fig 8-2 | 6 |
| Steady-state common-mode output voltage change | ΔVOC(SS) | -100 |  | 100 | mV |  | 6 |
| Driver short-circuit output current | IOSD | -200 |  | 200 | mA | DE = VCC, -65V ≤ VO ≤ 65V, or A and B shorted | 6 |
| Bus input current | II |  |  | 125 | μA | DE = 0V, VCC = 0V or 5.5V, VI = 12V | 6 |
| Bus input current | II | -100 |  |  | μA | DE = 0V, VCC = 0V or 5.5V, VI = -7V | 6 |
| Bus input current | II |  |  | 410 | μA | DE = 0V, VCC = 0V or 5.5V, VI = 40V | 6 |
| Bus input current | II | -400 |  |  | μA | DE = 0V, VCC = 0V or 5.5V, VI = -40V | 6 |
| Bus input impedance | RI | 96 |  |  | kΩ | Within common-mode voltage range | 6 |
| Common-mode voltage range | VCM | -25 |  | 25 | V | 3V ≤ VCC ≤ 3.6V | 6 |
| Common-mode voltage range | VCM | -40 |  | 40 | V | 4.5V ≤ VCC ≤ 5.5V | 6 |
| Positive input threshold voltage | VTH+ |  |  | -20 | mV | Within common-mode voltage range | 6 |
| Negative input threshold voltage | VTH- | -200 |  |  | mV | Within common-mode voltage range | 6 |
| Input hysteresis voltage | VHYS2 | 30 |  |  | mV |  | 6 |
| Output low-level voltage | VOL | 0.2 |  | 0.4 | V | IOL = 3mA | 6 |
| High-impedance output current | IOZR | -1 |  | 1 | μA | REB = VCC, VO = 0V or VCC | 6 |
| Receiver short-circuit output current | IOSR |  |  | 95 | mA | REB = DE = 0V, see Fig 8-3 | 6 |
| Input current (DI, DE, REB) | IIN | -10 |  | 10 | μA | 0V ≤ VIN ≤ VCC; for DE after hot-plug protection time | 6 |
| High-level input threshold (DI, DE, REB) | VIH | 2 |  |  | V |  | 6 |
| Low-level input threshold (DI, DE, REB) | VIL | 0 |  | 0.8 | V |  | 6 |
| Static supply current, driver and receiver enabled | ICC |  | 2.2 | 3.5 | mA | REB = 0V, DE = VCC, no load | 6 |
| Static supply current, driver enabled, receiver disabled | ICC |  | 2.2 | 3.5 | mA | REB = VCC, DE = VCC, no load | 6 |
| Static supply current, driver disabled, receiver enabled | ICC |  | 1.4 | 2.5 | mA | REB = 0V, DE = 0V, no load | 6 |
| Static supply current, driver and receiver disabled | ICC |  | 10 | 30 | μA | REB = VCC, DE = 0V, DI = VCC, no load | 6 |
| Thermal shutdown temperature | TSD |  | 185 |  | °C | Temperature rising | 6 |
| Thermal shutdown hysteresis |  |  | 20 |  | °C |  | 6 |
| Differential output rise/fall time | tDR, tDF |  | 110 | 500 | ns | RL = 54Ω, CL = 50pF, see Fig 8-4 | 7 |
| Driver propagation delay | tDPHL, tDPLH |  | 170 | 600 | ns |  | 7 |
| Driver pulse skew | tDSKEW |  | 5 | 50 | ns | /tDPHL, tDPLH/ | 7 |
| Driver disable time | tDHZ, tDLZ |  | 70 | 250 | ns | See Fig 8-5 and 8-6 | 7 |
| Driver enable time | tDZH, tDZL |  | 180 | 900 | ns | REB = 0V, see Fig 8-5 and 8-6 | 7 |
| Driver enable time from shutdown | tDZH(SHDN), tDZL(SHDN) |  | 3.3 | 8 | μs | REB = VCC, see Fig 8-5 and 8-6 | 7 |
| Receiver propagation delay | tRPHL, tRPLH |  | 145 | 300 | ns | CL = 15pF, see Fig 8-7 | 7 |
| Receiver pulse skew | tRSKEW |  | 3 | 30 | ns | /tRPHL, tRPLH/ | 7 |
| Receiver disable time | tRHZ, tRLZ |  | 10 | 80 | ns | See Fig 8-8 | 7 |
| Receiver enable time | tRZH, tRZL |  | 10 | 80 | ns | DE = VCC, see Fig 8-8 | 7 |
| Receiver enable time from shutdown | tRZH(SHDN), tRZL(SHDN) |  | 3.9 | 8 | μs | DE = 0V, see Fig 8-9 | 7 |
| Junction-to-ambient thermal resistance, SOIC8 | RθJA |  | 120 |  | °C/W |  | 5 |

## CAD (KiCad official)

- Symbol: `CA-IF4905S`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ca-if4905s-etched.step` / `ca-if4905s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-if4905s.step` / `ca-if4905s.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604440374123241472) (19 pp, sha256 `3042ede74dfad5c5`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ca-if4905s-datasheet.pdf)