CA-IF4888HS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RO	output	Receiver data output (digital output); high-impedance when REB is high, with output swing VOH ≥ VCC-0.4 V at IOH = -4 mA and VOL ≤ 0.4 V at IOL = 4 mA.
2	REB	input	Receiver enable input, active low; REB low enables the receiver, REB high or open puts RO in high impedance.
3	DE	input	Driver enable input, active high; has an internal pull-down so the driver is disabled (high-impedance) when open.
4	DI	input	Driver data input; has an internal pull-up to VCC so A is high and B low when floating with the driver enabled.
5	GND	power_in	Ground.
6	A	bidirectional	Driver output / receiver input A on the RS-485 bus, with ±30 kV HBM ESD, ±15 V common-mode range and ±30 V fault protection.
7	B	bidirectional	Driver output / receiver input B on the RS-485 bus, with ±30 kV HBM ESD, ±15 V common-mode range and ±30 V fault protection.
8	VCC	power_in	Power supply, 3 V to 5.5 V recommended operating range (absolute maximum 7.0 V).

Key specifications

Parameter	Value
Manufacturer	Chipanalog
Package	SOIC-8
Category	Interface
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.3		7	V		3
Bus pin voltage A,B	VIO	-30		30	V	A,B	3
Logic pin voltage DI,DE,REB	VIO	-0.3		7	V	DI,DE,REB	3
RO pin voltage (lower limit)	VIO	-0.3			V	RO; upper limit VCC+0.3 V	3
Junction temperature	TJ			150	°C		3
Storage temperature	TSTG	-65		150	°C		3
HBM ESD, bus pins	VESD	-30		30	kV	HBM, ANSI/ESDA/JEDEC JS-001, bus pins	3
HBM ESD, other pins	VESD	-6		6	kV	HBM, ANSI/ESDA/JEDEC JS-001, other pins	3
Supply voltage	VCC	3	5	5.5	V		4
Bus input voltage	VIN	-15		15	V		4
Low-level input threshold	VIL	0		0.8	V		4
High-level input threshold (lower limit)	VIH	2			V	upper limit VCC	4
Differential load resistance	RL	54			Ohm		4
Data rate	1/tUI			500	kbps		4
Ambient temperature	TA	-40		125	°C		4
Junction temperature	TJ	-40		150	°C		4
Junction-to-ambient thermal resistance	RθJA		115		°C/W	SOIC8	4
Junction-to-case (top) thermal resistance	RθJC		60		°C/W	SOIC8	4
Differential output voltage	/VOD/	1.5	3.5		V	RL =60 Ω, -15 V ≤ Vtest ≤ 15 V	5
Differential output voltage	/VOD/	2.1			V	RL =60 Ω, -15 V ≤ Vtest ≤ 15 V, 4.5 V ≤ VCC ≤ 5.5 V	5
Differential output voltage	/VOD/	2	4		V	RL = 100 Ω	5
Differential output voltage	/VOD/	1.5	3.7		V	RL = 54 Ω	5
Change in differential output voltage	Δ/VOD/	-200		200	mV	RL = 54 Ω	5
Common-mode output voltage	VOC	1		3	V		5
Change in common-mode output voltage	ΔVOC(SS)	-200		200	mV		5
Short-circuit output current	IOS	-250		250	mA	-7 V ≤ VO ≤ 12 V	5
Bus input current	II		72	125	μA	DE = 0 V, VCC = 0 V or 5 V, VI = 12V	5
Bus input current	II	-100	-43		μA	DE = 0 V, VCC = 0 V or 5 V, VI = -7V	5
Bus input current	II		91	125	μA	DE = 0 V, VCC = 0 V or 5V, VI = 15V	5
Bus input current	II	-200	-97		μA	DE = 0 V, VCC = 0 V or 5V, VI = -15V	5
Positive-going input threshold voltage	VTH+	-100		-20	mV	Within common-mode range	5
Negative-going input threshold voltage	VTH-	-200		-130	mV	Within common-mode range	5
Input hysteresis voltage	VHYS		30		mV		5
Output low voltage	VOL		0.2	0.4	V	IOL = 4 mA	5
Output high-impedance current	IOZR	-1		1	μA	VO = 0 V or VCC, REB= VCC	5
Logic input current	IIN	-6.2		6.2	μA	3 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC	5
Supply current, driver and receiver enabled	ICC		2.4	3	mA	REB=0V, DE = VCC, no load	5
Supply current, driver enabled, receiver off	ICC		0.8	1.2	mA	REB=VCC, DE = VCC, no load	5
Supply current, driver off, receiver enabled	ICC		700	960	μA	REB=0V, DE = 0V, no load	5
Supply current, driver and receiver off	ICC		2.4	5	μA	REB=VCC, DE = 0V, DI=open, no load	5
Thermal shutdown temperature	TSD		180		°C		5
Driver rise/fall time	tr, tf	250	360	680	ns	RL = 54 Ω, CL = 50 pF	6
Driver propagation delay	tPHL, tPLH		280	500	ns	RL = 54 Ω, CL = 50 pF	6
Driver pulse skew	tSK(P)			10	ns	/tPHL, tPLH/	6
Driver disable time	tPHZ, tPLZ		10	200	ns	RL = 54 Ω, CL = 50 pF	6
Driver enable time	tPZH, tPZL		100	600	ns	REB = 0 V	6
Driver enable time	tPZH, tPZL		7.2	11	μs	REB = VCC	6
Receiver rise/fall time	tr, tf		3.8	10	ns	CL = 15 pF	6
Receiver propagation delay	tPHL, tPLH		23	110	ns	CL = 15 pF	6
Receiver pulse skew	tSK(P)			7	ns	/tPHL, tPLH/	6
Receiver disable time	tPHZ, tPLZ		7	20	ns	CL = 15 pF	6
Receiver enable time	tPZH(1), tPZL(1)		8	20	ns	DE = VCC	6
Receiver enable time	tPZH(2), tPZL(2)		7	14	μs	DE = 0 V	6
Bus failsafe time	tFS	38	76	114	ms	Driver disabled	6

CAD (KiCad official)

Symbol: CA-IF4888HS
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: ca-if4888hs-etched.step / ca-if4888hs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-if4888hs.step / ca-if4888hs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Chipanalog datasheet (16 pp, sha256 cfae97ab1df30445, retrieved 2026-10-30, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CA-IF4888HS

Verified CA-IF4888HS

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README