CA-IF4820HS

{
  "schema_version": 1,
  "type": "component",
  "slug": "ca-if4820hs",
  "title": "CA-IF4820HS",
  "brief": "Chipanalog RS-485 / RS-422 ICs, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "interface",
    "ca-if4820hs"
  ],
  "component": {
    "mpn": "CA-IF4820HS",
    "manufacturer": "Chipanalog",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Interface",
    "subcategory": "RS-485 / RS-422 ICs",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/6dd14e0b105fe2b3868ddaf42150e021.pdf",
    "parts": {
      "symbol": "ca-if4820hs.kicad_sym",
      "footprint": "ca-if4820hs.kicad_mod",
      "model_3d": "ca-if4820hs-etched.glb",
      "model_3d_plain": "ca-if4820hs.glb",
      "model_3d_step": "ca-if4820hs-etched.step",
      "model_3d_step_plain": "ca-if4820hs.step",
      "lbr": "ca-if4820hs.lbr"
    },
    "distributor_links": {
      "lcsc": "C2846827"
    },
    "pins": [
      {
        "number": "1",
        "name": "RO",
        "type": "output",
        "description": "Receiver bus output. Digital CMOS output that presents the recovered logic level from the differential A/B bus to the host controller when the receiver is enabled (REB=0)."
      },
      {
        "number": "2",
        "name": "REB",
        "type": "input",
        "description": "Receiver enable, active-low. Drive REB low to enable the receiver output (RO); drive REB high to place RO in high-impedance. Digital CMOS input referenced to VCC/GND."
      },
      {
        "number": "3",
        "name": "DE",
        "type": "input",
        "description": "Driver enable, active-high. Drive DE high to enable the differential driver onto the A/B bus; drive DE low to place the driver outputs in high-impedance (allowing multipoint bus sharing)."
      },
      {
        "number": "4",
        "name": "DI",
        "type": "input",
        "description": "Driver bus input. Digital CMOS input; the logic level on DI is transmitted as the differential state on A/B when DE is asserted."
      },
      {
        "number": "5",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference for logic and bus circuitry."
      },
      {
        "number": "6",
        "name": "A",
        "type": "bidirectional",
        "description": "Non-inverting RS-485/RS-422 bus line. Serves as the driver's non-inverting output when DE=1 and as the receiver's non-inverting input when REB=0. ±15V common-mode range; ±30V fault protection; ±30kV HBM ESD."
      },
      {
        "number": "7",
        "name": "B",
        "type": "bidirectional",
        "description": "Inverting RS-485/RS-422 bus line. Serves as the driver's inverting output when DE=1 and as the receiver's inverting input when REB=0. ±15V common-mode range; ±30V fault protection; ±30kV HBM ESD."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage input, 3.0V to 5.5V. Bypass to GND with a local decoupling capacitor."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/6dd14e0b105fe2b3868ddaf42150e021.pdf",
        "pages": 21,
        "sha256": "c063fe96e2b8699c",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -1.905
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
      "mark": "drawn"
    },
    "models_3d": [
      {
        "file": "ca-if4820hs.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ca-if4820hs-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "cd5e9714ec2ee3b3b354b8a716461c480875e4f1909fd7fea6bdade538963b0c",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Chipanalog",
      "Package": "SOIC-8",
      "Category": "Interface",
      "Pins": "8"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "ca-if4820hs"
  ],
  "discovery_pitch": "CA-IF4820HS (Chipanalog) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ca-if4820hs.kicad_sym",
    "ca-if4820hs.kicad_mod",
    "ca-if4820hs.glb",
    "ca-if4820hs.step",
    "ca-if4820hs-etched.step",
    "ca-if4820hs.lbr",
    "docs/hero.png",
    "docs/ca-if4820hs-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "updated_at": "2026-09-24T18:23:48.682Z"
}