CA-IF4820FS

{
  "schema_version": 1,
  "type": "component",
  "slug": "ca-if4820fs",
  "title": "CA-IF4820FS",
  "brief": "Chipanalog RS-485/RS-422 ICs, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "comm-uart",
    "ca-if4820fs"
  ],
  "component": {
    "mpn": "CA-IF4820FS",
    "manufacturer": "Chipanalog",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Comm/UART",
    "subcategory": "RS-485/RS-422 ICs",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403291734_Chipanalog-CA-IF4820FS_C7422521.pdf",
    "parts": {
      "symbol": "ca-if4820fs.kicad_sym",
      "footprint": "ca-if4820fs.kicad_mod",
      "model_3d": "ca-if4820fs-etched.glb",
      "model_3d_plain": "ca-if4820fs.glb",
      "model_3d_step": "ca-if4820fs-etched.step",
      "model_3d_step_plain": "ca-if4820fs.step",
      "lbr": "ca-if4820fs.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage input, 3.0 V to 5.5 V. Requires at least a 0.1 µF decoupling capacitor between VCC and GND placed close to the pin."
      },
      {
        "number": "2",
        "name": "RO",
        "type": "output",
        "description": "Receiver digital output. RO = high when (VA - VB) > VTH+; RO = low when (VA - VB) < VTH-. CMOS logic, VOH ≥ VCC-0.4 V at -4 mA, VOL ≤ 0.4 V at 4 mA."
      },
      {
        "number": "3",
        "name": "DI",
        "type": "input",
        "description": "Driver data input. When DI is high, Y outputs high and Z outputs low; when DI is low, Y outputs low and Z outputs high. CMOS logic input."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "5",
        "name": "Y",
        "type": "output",
        "description": "RS-485/RS-422 driver non-inverting differential output. Absolute max bus voltage ±30 V, common-mode operating range -7 V to +12 V."
      },
      {
        "number": "6",
        "name": "Z",
        "type": "output",
        "description": "RS-485/RS-422 driver inverting differential output. Absolute max bus voltage ±30 V, common-mode operating range -7 V to +12 V."
      },
      {
        "number": "7",
        "name": "B",
        "type": "input",
        "description": "RS-485/RS-422 receiver inverting differential input. Absolute max bus voltage ±30 V, common-mode operating range -7 V to +12 V."
      },
      {
        "number": "8",
        "name": "A",
        "type": "input",
        "description": "RS-485/RS-422 receiver non-inverting differential input. Absolute max bus voltage ±30 V, common-mode operating range -7 V to +12 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403291734_Chipanalog-CA-IF4820FS_C7422521.pdf",
        "pages": 24,
        "sha256": "2bf29538f533f541",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ca-if4820fs.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ca-if4820fs-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "8919f3f4b3546c780931febd060d5b7f9b2fb41ae7f3303abf2dc61e1de30d90",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Chipanalog",
      "Package": "SOIC-8",
      "Category": "Comm/UART",
      "Pins": "8"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "ca-if4820fs"
  ],
  "discovery_pitch": "CA-IF4820FS (Chipanalog) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ca-if4820fs.kicad_sym",
    "ca-if4820fs.kicad_mod",
    "ca-if4820fs.glb",
    "ca-if4820fs.step",
    "ca-if4820fs.lbr",
    "docs/hero.png",
    "docs/ca-if4820fs-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ca-if4820fs-etched.step"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "CA-IF4820FS",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IF4820FSFM",
      "kind": "packaging"
    },
    {
      "mpn": "CA-IF4820FSFD",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T18:23:32.990Z"
}