CA-IF4420S

{
  "schema_version": 1,
  "type": "component",
  "slug": "ca-if4420s",
  "title": "CA-IF4420S",
  "brief": "Chipanalog RS-485/RS-422 ICs, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "comm-uart",
    "ca-if4420s"
  ],
  "component": {
    "mpn": "CA-IF4420S",
    "manufacturer": "Chipanalog",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Comm/UART",
    "subcategory": "RS-485/RS-422 ICs",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403291734_Chipanalog-CA-IF4420S_C7422518.pdf",
    "parts": {
      "symbol": "ca-if4420s.kicad_sym",
      "footprint": "ca-if4420s.kicad_mod",
      "model_3d": "ca-if4420s-etched.glb",
      "model_3d_plain": "ca-if4420s.glb",
      "model_3d_step": "ca-if4420s-etched.step",
      "model_3d_step_plain": "ca-if4420s.step",
      "lbr": "ca-if4420s.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "TXD",
        "type": "input",
        "description": "Transmit data input. TXD high drives the CAN bus recessive; TXD low drives the bus dominant. Internally pulled up to VIO."
      },
      {
        "number": "2",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference."
      },
      {
        "number": "3",
        "name": "VCC",
        "type": "power_in",
        "description": "5 V bus-side supply input (4.5 V to 5.5 V recommended). Bypass with a 0.1 µF ceramic capacitor placed close to the pin between VCC and GND."
      },
      {
        "number": "4",
        "name": "RXD",
        "type": "output",
        "description": "Receiver data output. High when the CAN bus is recessive, low when the bus is dominant. Output is referenced to VIO."
      },
      {
        "number": "5",
        "name": "VIO",
        "type": "power_in",
        "description": "I/O supply for logic-level translation (1.7 V to 5.5 V). Sets the reference for TXD, RXD, and POL logic thresholds so the transceiver can interface with 1.8 V / 2.5 V / 3.3 V / 5 V controllers."
      },
      {
        "number": "6",
        "name": "CANL",
        "type": "bidirectional",
        "description": "Low-side CAN bus I/O. Tolerates ±58 V bus fault voltage and ±30 V receiver common-mode range."
      },
      {
        "number": "7",
        "name": "CANH",
        "type": "bidirectional",
        "description": "High-side CAN bus I/O. Tolerates ±58 V bus fault voltage and ±30 V receiver common-mode range."
      },
      {
        "number": "8",
        "name": "POL",
        "type": "input",
        "description": "Polarity control input. POL = low selects normal (default) CAN bus polarity; POL = high inverts the CANH/CANL polarity. Referenced to VIO logic levels."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2403291734_Chipanalog-CA-IF4420S_C7422518.pdf",
        "pages": 20,
        "sha256": "b6a5642576e922f3",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ca-if4420s.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ca-if4420s-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "1c63fcd103c8d75fea9c7c95364de45e472e2558f02845632d4818ed28d75e3f",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Chipanalog",
      "Package": "SOIC-8",
      "Category": "Comm/UART",
      "Pins": "8"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "ca-if4420s"
  ],
  "discovery_pitch": "CA-IF4420S (Chipanalog) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ca-if4420s.kicad_sym",
    "ca-if4420s.kicad_mod",
    "ca-if4420s.glb",
    "ca-if4420s.step",
    "ca-if4420s.lbr",
    "docs/hero.png",
    "docs/ca-if4420s-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ca-if4420s-etched.step"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "CA-IF4420S",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T18:23:25.089Z"
}