component
CA-IF4289
Public Made by Adomby adom
Chipanalog Buffers, Drivers, Receivers, Transceivers, QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IF4289
Chipanalog · Buffers, Drivers, Receivers, Transceivers · QFN-24(4x4)
CA-IF4289 from Chipanalog, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DOUT | output | Open-drain logic data output that requires a pull-up resistor to the logic supply; DOUT goes high when the AIO-BIO edge crosses VTVL and goes high-impedance when the trailing edge crosses VTVT. |
| 2 | DIN | input | Logic data input; DIN high-to-low reverses the polarity of AIO and BIO, and DIN low-to-high puts AIO and BIO in high impedance. |
| 3 | RST | input | Bus reset control input; pulling RST low enables the transmitter on AIO and BIO and pulling it high disables it, and RST also controls the dynamic termination switch. |
| 4 | NC | unconnected | No connection. |
| 5 | /PG_P | output | Open-drain active-low output that indicates the bus is powered with positive polarity (VHP-VHN > 3V). |
| 6 | /PG_N | output | Open-drain active-low output that indicates the bus is powered with negative polarity (VHN-VHP > 3V). |
| 7 | BIO | bidirectional | Home bus data input/output; in 57.6kbps applications it connects to the bus through a 1 uF capacitor in series with a 4.7 Ohm resistor. |
| 8 | HN | input | Home bus interface pin that must be connected to the bus through a series resistor of about 200 Ohm to limit surge voltage. |
| 9 | GND | power_in | Ground reference pin; star-connect all grounds close to this pin. |
| 10 | HP | input | Home bus interface pin that must be connected to the bus through a series resistor of about 200 Ohm to limit surge voltage. |
| 11 | AIO | bidirectional | Home bus data input/output; in 57.6kbps applications it connects to the bus through a 1 uF capacitor in series with a 4.7 Ohm resistor. |
| 12 | TERM | output | Switchable bus termination; a resistor (typically 100 Ohm, recommended 50 to 240 Ohm) is connected between TERM and BIO to match cable termination impedance. |
| 13 | EN_VT | input | Active-high internal receiver threshold enable; when high, internal TVL (2.0 V typ.) and TVT (1.5 V typ.) are used, and it has an internal 1 MOhm pulldown and is disabled if left floating. |
| 14 | NC | unconnected | No connection. |
| 15 | NC | unconnected | No connection. |
| 16 | GND | power_in | Ground reference pin. |
| 17 | VCC | power_in | Chip supply input; operating range 4.5 V to 5.5 V (5 V typ.). |
| 18 | VCC | power_in | Chip supply input; operating range 4.5 V to 5.5 V (5 V typ.). |
| 19 | WT_ENb | input | Active-low DIN low-timeout protection enable; when low, AIO/BIO go high-impedance after DIN has been low for more than 21 ms, and the pin has an internal 180 kOhm pulldown so it is enabled if left floating. |
| 20 | HPEN | input | High-pass filter enable: connect to VCC to enable the receiver high-pass filter or to GND to disable it; do not leave it floating. |
| 21 | TVL | input | Leading-edge receiver threshold input; must satisfy VTVL > VTVT when external thresholds are used (EN_VT low). |
| 22 | TVT | input | Trailing-edge receiver threshold input; must be lower than TVL (recommended VTVT of 1.5 V minimum per the recommended operating conditions). |
| 23 | SRA | input | Slew-rate adjust input; a resistor from SRA to GND sets the AIO/BIO edge slope, with RSRA recommended between 20 kOhm and 120 kOhm (33 kOhm typical). |
| 24 | DTA | input | Bus dynamic termination time adjust; an external 10 kOhm to 500 kOhm resistor to GND sets the termination on-time (about 10 us to 500 us), and when floating the on-time is 34 us. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | QFN-24(4x4) |
| Category | Logic |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Vcc 到 GND | Vcc | -0.3 | 6 | V | 7 | ||
| AIO,BIO,TERM,SRA 到 GND | -0.3 | V | 7 | ||||
| HP、HN 到 GND | -0.3 | 28 | V | 7 | |||
| HP 到 HN 差分 | -28 | 28 | V | 7 | |||
| VCC,AIO,BIO,TERM 端口连续电流 | -100 | 100 | mA | 7 | |||
| 其他管脚连续电流 | -50 | 50 | mA | 7 | |||
| 正常工作温度范围 | -40 | 105 | °C | 7 | |||
| 存储温度范围 | -40 | 150 | °C | 7 | |||
| 结温 | 150 | °C | 7 | ||||
| 焊接温度 | 260 | °C | 7 | ||||
| VCC 电源电压 (建议工作条件) | VCC | 4.5 | 5 | 5.5 | V | 8 | |
| TA 环境温度 | TA | -40 | 25 | 105 | °C | 8 | |
| Vcc 电源电压 | Vcc | 4.5 | 5 | 5.5 | V | 9 | |
| UVLO 电压 Vcc 电压上升 | VUV | 4 | 4.2 | 4.4 | V | 9 | |
| 终端开关导通电阻 | RTERM | 2.5 | 5 | 10 | Ω | TERM 到 AIO | 9 |
| AIO,BIO 发射输入电阻 | RIN | 7 | 10 | 13 | kΩ | AIO,BIO 悬空时的输入电阻，DIN=Vcc | 9 |
| 偏置电压匹配比例 | VAIO/ VBIO | -1 | 1 | % | AIO,BIO 悬空 | 9 | |
| 接收端前沿阈值 | VLEAD | 0.85 | 1 | 1.15 | V | VTVL = 1.0V, HPEN = Vcc | 9 |
| 接收端后沿阈值 | VTRAIL | 0.35 | 0.5 | 0.65 | V | VTVT = 0.5V, HPEN =Vcc | 9 |
| 内部高电平阈值 | VTVL | 1.8 | 2 | 2.2 | V | EN_VT=high | 9 |
| 内部低电平阈值 | VTVT | 1.3 | 1.5 | 1.7 | V | EN_VT=high | 9 |
| TVL,TVT 输入漏电流 | ITHLEAK | -1 | 1 | μA | VTVL = VTVT = 2.5V | 9 | |
| 输入端漏电流 | ILEAK | -1 | 1 | μA | 9 | ||
| 终端导通时间 | tTRMON | 19 | 34 | 63 | μs | RSRA=62kΩ，RLOAD=200Ω | 10 |
| 最小终端导通时间 | tTRMON_min | 8 | 10 | 12 | μs | RSRA=62kΩ，RLOAD=200Ω，DTA connect 10kΩ resistor | 10 |
| 最大终端导通时间 | tTRMON_max | 400 | 500 | 600 | μs | RSRA=62kΩ，RLOAD=200Ω，DTA connect 500kΩ resistor | 10 |
| 传输输出对称性 | tSYM | -0.4 | 0 | 0.4 | μs | RSRA=62kΩ， RLOAD=200Ω | 10 |
| 总线高电平检测电压 | Vhigh | 2.5 | 3 | 3.5 | V | HP-HN 电压上升直到/PG_P 变低时的值 | 10 |
| 总线低电平检测电压 | Vlow1 | 2.5 | 3 | 3.5 | V | HN-HP 电压 上升直到/PG_N 变低时的值 | 10 |
CAD (KiCad official)
- Symbol:
CA-IF4289 - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
ca-if4289-etched.step/ca-if4289-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-if4289.step/ca-if4289.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (20 pp, sha256
fd4e29ca379c5af9, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).