component
CA-IF4288
Public Made by Adomby adom
Chipanalog Buffer/Driver/Transceiver, QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCA-IF4288
Chipanalog · Buffer/Driver/Transceiver · QFN-24(4x4)
CA-IF4288 from Chipanalog, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DOUT | output | Open-drain data output, connect a pull-up resistor to the logic supply. |
| 2 | DIN | input | Data input; a high-to-low transition reverses AIO/BIO polarity and low-to-high puts them in high impedance. |
| 3 | RST | input | Bus reset control input; low enables the transmitter to AIO/BIO, high disables it and opens the internal termination switch. |
| 4 | NC | unconnected | No connection. |
| 5 | NC | unconnected | No connection. |
| 6 | NC | unconnected | No connection. |
| 7 | BIO | bidirectional | Home bus data input/output; in 57.6kbps applications it connects to the home bus through a 1uF capacitor in series with a 4.7 ohm resistor. |
| 8 | NC | unconnected | No connection. |
| 9 | GND | power_in | Reference ground. |
| 10 | NC | unconnected | No connection. |
| 11 | AIO | bidirectional | Home bus data input/output; in 57.6kbps applications it connects to the home bus through a 1uF capacitor in series with a 4.7 ohm resistor. |
| 12 | TERM | output | Switchable bus termination; a resistor between TERM and BIO sets the cable termination impedance match. |
| 13 | NC | unconnected | No connection. |
| 14 | NC | unconnected | No connection. |
| 15 | NC | unconnected | No connection. |
| 16 | GND | power_in | Reference ground. |
| 17 | VCC | power_in | Chip power supply input, 4.5V to 5.5V recommended. |
| 18 | VCC | power_in | Chip power supply input, 4.5V to 5.5V recommended. |
| 19 | WT_ENb | input | Active-low enable of the DIN low-level timeout protection, with internal 180 kohm pull-down so it is enabled by default when floating. |
| 20 | NC | unconnected | No connection on CA-IF4288 (this pin is HPEN on CA-IF4289). |
| 21 | TVL | input | Leading-edge data threshold input that sets the receiver leading-edge threshold voltage. |
| 22 | TVT | input | Trailing-edge data threshold input that sets the receiver trailing-edge threshold voltage. |
| 23 | SRA | input | Slew rate adjust input; a resistor to GND (recommended 33 kohm, 20 kohm to 120 kohm range) sets the AIO/BIO transmit edge slope. |
| 24 | NC | unconnected | No connection on CA-IF4288 (this pin is DTA on CA-IF4289). |
| 25 | EP | passive | Exposed pad, connect to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | QFN-24(4x4) |
| Category | Logic |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage to GND | Vcc | -0.3 | 6 | V | Vcc to GND | 7 | |
| AIO,BIO,TERM,SRA to GND | -0.3 | V | max printed as Vcc+0.3 | 7 | |||
| HP, HN to GND | -0.3 | 28 | V | 7 | |||
| HP to HN differential | -28 | 28 | V | 7 | |||
| VCC,AIO,BIO,TERM continuous current | -100 | 100 | mA | 7 | |||
| Other pins continuous current | -50 | 50 | mA | 7 | |||
| Normal operating temperature range | -40 | 105 | °C | 7 | |||
| Junction temperature | 150 | °C | 7 | ||||
| Storage temperature range | -40 | 150 | °C | 7 | |||
| Soldering temperature | 260 | °C | 7 | ||||
| ESD HBM all pins | ESD-HBM | -6 | 6 | kV | ANSI/ESDA/JEDEC JS-001, all pins | 8 | |
| ESD HBM AIO,BIO to GND | -30 | 30 | kV | JS-001, AIO,BIO to GND | 8 | ||
| ESD CDM all pins | -2 | 2 | kV | ANSI/ESDA/JEDEC JS-002 | 8 | ||
| IEC 61000-4-2 air discharge | -15 | 15 | kV | AIO,BIO,TERM to GND | 8 | ||
| IEC 61000-4-2 contact discharge | -8 | 8 | kV | AIO,BIO,TERM to GND | 8 | ||
| Supply voltage | VCC | 4.5 | 5 | 5.5 | V | 8 | |
| Ambient temperature | TA | -40 | 25 | 105 | °C | 8 | |
| Junction temperature | TJ | 150 | °C | 8 | |||
| Junction-to-ambient thermal resistance | RθJA | 52 | °C/W | QFN | 8 | ||
| Supply voltage | Vcc | 4.5 | 5 | 5.5 | V | 9 | |
| Supply current | ICC | 1.7 | 2.5 | mA | VCC=5.0V, no load, 57.6kbps, CL=0pF | 9 | |
| UVLO voltage | VUV | 4 | 4.2 | 4.4 | V | Vcc rising | 9 |
| UVLO hysteresis | VUV_hys | 100 | mV | 9 | |||
| Output low level | VTOL | 0.6 | V | AIO,BIO to GND, Iload=45mA to Vcc | 9 | ||
| Termination switch on-resistance | RTERM | 2.5 | 5 | 10 | Ω | TERM to AIO | 9 |
| AIO,BIO transmit input resistance | RIN | 7 | 10 | 13 | kΩ | AIO,BIO floating, DIN=Vcc | 9 |
| Bias voltage matching ratio | VAIO/VBIO | -1 | 1 | % | AIO,BIO floating | 9 | |
| Receiver leading edge threshold | VLEAD | 0.85 | 1 | 1.15 | V | VTVL = 1.0V, HPEN = Vcc | 9 |
| Receiver trailing edge threshold | VTRAIL | 0.35 | 0.5 | 0.65 | V | VTVT = 0.5V, HPEN =Vcc | 9 |
| Internal high threshold | VTVL | 1.8 | 2 | 2.2 | V | EN_VT=high | 9 |
| Internal low threshold | VTVT | 1.3 | 1.5 | 1.7 | V | EN_VT=high | 9 |
| TVL,TVT input leakage current | ITHLEAK | -1 | 1 | μA | VTVL = VTVT = 2.5V | 9 | |
| Input logic high level | VIH | 1.4 | V | 9 | |||
| Input logic low level | VIL | 0.4 | V | 9 | |||
| Input leakage current | ILEAK | -1 | 1 | μA | 9 | ||
| Open-drain logic low level | VOL | 0.3 | V | ISINK=2mA | 9 | ||
| Open-drain leakage current | VODL | 1 | μA | Vout=5V, output not pulled low | 9 | ||
| Transmit output symmetry | tSYM | -0.4 | 0 | 0.4 | μs | RSRA=62kΩ, RLOAD=200Ω | 10 |
| Termination on time | tTRMON | 19 | 34 | 63 | μs | RSRA=62kΩ, RLOAD=200Ω | 10 |
| Minimum termination on time | tTRMON_min | 8 | 10 | 12 | μs | RSRA=62kΩ, RLOAD=200Ω, DTA connect 10kΩ resistor | 10 |
| Maximum termination on time | tTRMON_max | 400 | 500 | 600 | μs | RSRA=62kΩ, RLOAD=200Ω, DTA connect 500kΩ resistor | 10 |
CAD (KiCad official)
- Symbol:
CA-IF4288 - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
ca-if4288-etched.step/ca-if4288-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ca-if4288.step/ca-if4288.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Chipanalog datasheet (20 pp, sha256
fd4e29ca379c5af9, retrieved 2026-10-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).