# CA-IF42088

**Chipanalog** · Buffers, Drivers, Receivers, Transceivers · QFN-24-EP(4x4)

CA-IF42088 from Chipanalog, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DOUT | output | Open-drain digital output that needs an external pull-up to the logic supply, with VOL of 0.3 V max at 2 mA sink and leakage of 1 µA max when open. |
| 2 | DIN | input | Digital data input from the MCU, with VIH minimum 1.4 V and VIL maximum 0.4 V. |
| 3 | RST | input | Active-low bus reset control input: low enables the transmitter and high puts it in high impedance, and RST also controls the internal dynamic termination. |
| 4 | CAPN | input | Active-inductor control port on the HN side; in bus-powered use the capacitance between CAPN and HNA sets the equivalent inductance, and in non-bus-powered use CAPN is shorted to HNA to bypass the inductor. |
| 5 | HNA | input | Active-inductor control port on the HN side; in bus-powered use the capacitance between HNA and CAPN sets the equivalent inductance, and in non-bus-powered use HNA is shorted to CAPN to bypass the inductor. |
| 6 | NC | unconnected | No internal connection. |
| 7 | BIO | bidirectional | One of the differential transceiver data ports to the Home Bus, coupled through external capacitors, with absolute maximum AIO/BIO voltage of VCC + 0.3 V to GND. |
| 8 | HN | power_in | Negative bus-power terminal and one of the differential data ports of the Home Bus, with absolute maximum HN to GND of ±6.0 V. |
| 9 | GND | power_in | Internal reference ground that floats with respect to HN in bus-powered applications and connects to HN in non-bus-powered applications; keep it close to the device's ground connections. |
| 10 | HP | power_in | Positive bus-power terminal and one of the differential data ports of the Home Bus, with absolute maximum HP to GND of +28 V and VHP-VHN of 9 V to 24 V for bus powering. |
| 11 | AIO | bidirectional | One of the differential transceiver data ports to the Home Bus, coupled through external capacitors, with absolute maximum AIO/BIO voltage of VCC + 0.3 V to GND. |
| 12 | TERM | output | Dynamic termination control port; a resistor between TERM and BIO sets the cable termination impedance, typically recommended between 50 Ω and 240 Ω. |
| 13 | NC | unconnected | No internal connection. |
| 14 | HPA | input | Active-inductor control port on the HP side; in bus-powered use the capacitance between CAPP and HPA sets the equivalent inductance, and in non-bus-powered use HPA is shorted to CAPP to bypass the inductor. |
| 15 | CAPP | input | Active-inductor control port on the HP side; in bus-powered use the capacitance between CAPP and HPA sets the equivalent inductance, and in non-bus-powered use CAPP is shorted to HPA to bypass the inductor. |
| 16 | GND | power_in | Internal reference ground that floats with respect to HN in bus-powered applications and connects to HN in non-bus-powered applications; keep it close to the device's ground connections. |
| 17 | VCC | power_out | Output of the internal 5 V LDO, which supplies up to 90 mA to external loads and needs at least 1 µF to GND placed as close to the device as possible. |
| 18 | VRAW | power_out | Active-inductor power output that supplies up to 300 mA; bypass with at least 100 µF to GND for loads below 70 mA or at least 200 µF to GND for loads above 70 mA. |
| 19 | EN | input | LDO enable input: connect to VRAW to enable the internal LDO, or connect to GND to disable it. |
| 20 | HPEN | input | Receiver high-pass filter enable input (overbar in the datasheet, so active low): connect to GND to enable the high-pass filter and to VCC to disable it, and do not leave it floating. |
| 21 | TVL | input | Receiver leading-edge data threshold input, which must be set higher than TVT (VTVL > VTVT), with recommended value of 0.5 V minimum per the recommended operating conditions. |
| 22 | TVT | input | Receiver trailing-edge data threshold input, which must be set lower than TVL (VTVL > VTVT). |
| 23 | SRA | input | Transmit output slew-rate adjust port; a resistor from SRA to GND sets the AIO and BIO edge slope, with RSRA specified between 33 kΩ and 470 kΩ. |
| 24 | DTA | input | Dynamic-termination enable-time adjust port; a 10 kΩ to 500 kΩ resistor to GND sets the termination time, and leaving it open gives 34 µs typical. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Chipanalog |
| Package | QFN-24-EP(4x4) |
| Category | Logic |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| HP to GND |  | -0.3 |  | 28 | V |  | 7 |
| HN to GND |  | -6 |  | 6 | V |  | 7 |
| HP to HN |  | -0.3 |  | 28 | V |  | 7 |
| HPA to CAPP, CAPN to HNA |  | -0.3 |  | 6 | V |  | 7 |
| VRAW, EN to GND |  | -0.3 |  | 28 | V |  | 7 |
| VCC to GND |  | -0.3 |  | 6 | V |  | 7 |
| AIO, BIO, TERM, SRA to GND |  | -0.3 |  |  | V |  | 7 |
| DIN, DOUT, TVL, TVT, RST, HPEN to GND |  | -0.3 |  | 6 | V |  | 7 |
| VCC, AIO, BIO, TERM continuous current |  | -100 |  | 100 | mA |  | 7 |
| HP, HN, VRAW, GND continuous current |  | -350 |  | 350 | mA |  | 7 |
| CAPP, CAPN continuous current |  | -10 |  | 10 | mA |  | 7 |
| Other pins continuous current |  | -50 |  | 50 | mA |  | 7 |
| Normal operating temperature range |  | -40 |  | 105 | °C |  | 7 |
| Junction temperature |  | -40 |  | 150 | °C |  | 7 |
| Storage temperature range |  | -40 |  | 150 | °C |  | 7 |
| Soldering temperature |  |  |  | 260 | °C |  | 7 |
| VHP, VHN bus supply voltage | VHP, VHN | 9 |  | 24 | V |  | 7 |
| TA ambient operating temperature | TA | -40 | 25 | 105 | °C |  | 7 |
| TJ junction temperature | TJ | -40 |  | 150 | °C |  | 7 |
| Receiver front-edge threshold | VTVL |  | 0.5 |  | V |  | 7 |
| Receiver trailing-edge threshold | VTVT |  | 1 |  | V |  | 7 |
| Slew-rate adjustment resistor | RSRA |  | 120 |  | kΩ |  | 7 |
| Junction-to-ambient thermal resistance (QFN24) | RθJA |  | 48 |  | °C/W |  | 7 |
| VHP, VHN bus-powered supply voltage | VHP, VHN | 9 |  | 24 | V | DC input voltage (excluding superimposed HBS data signal) | 8 |
| VRAW output voltage, bus-powered | VRAWO | 7.1 |  | 7.5 | V | VHP, VHN = 9V, IRAW = 0mA | 8 |
| VRAW output voltage, bus-powered at 300mA | VRAWO | 6 |  | 6.9 | V | VHP, VHN = 9V, IRAW = 300mA | 8 |
| VRAW supply voltage (external) | VRAWI | 4.6 |  | 24 | V | External voltage applied to VRAW | 8 |
| VCC output voltage | VCC | 4.5 | 5 | 5.5 | V | ILOAD = 90mA, VRAW ≥ 6V | 8 |
| Bus-powered VCC maximum load current | IVCCMAX |  |  | 90 | mA | VHP, VHN ≥ 9V | 8 |
| VRAW-powered VCC maximum load current | IVCCMAX |  |  | 90 | mA | VRAW ≥ 6V | 8 |
| VRAW maximum load current | IVRAWMAX |  |  | 300 | mA | VHP, VHN ≥ 9V, excluding superimposed HBS data signal | 8 |
| VRAW maximum load current with HBS data | IVRAWMAX |  |  | 300 | mA | VHP, VHN ≥ 9V, including superimposed 57.6kbps HBS data signal | 8 |
| Bus-powered quiescent current | IHP, IHN |  | 3 | 5 | mA | RST = VCC, ICC = 0mA, VHP, VHN = 9V | 8 |
| VRAW-powered quiescent current | IRAW |  | 2.5 | 4 | mA | RST = VCC, HP = CAPP = VRAW, HN = CAPN = GND | 8 |
| VRAW-powered dynamic current | IRAW |  | 28 |  |  | HP = CAPP = VRAW, VRST = HN = CAPN = GND, DIN 57.6kbps, RLOAD = 100Ω | 8 |
| Transmitter output high level | VTOH |  | 4.8 |  | V | VRAW ≥ 4.6V, AIO and BIO pull-up capability | 8 |
| Transmitter output low level | VTOL |  | 0.3 | 0.6 | V | VRAW ≥ 4.6V, AIO and BIO pull-down capability | 8 |
| Terminal switch on-resistance (TERM to AIO) | RTERM | 2 | 5 | 10 | Ω | TERM to AIO resistance | 8 |
| AIO, BIO transmit input resistance | RIN | 7 | 9 | 13 | kΩ | AIO, BIO floating, DIN = VCC | 8 |
| VAIO / VBIO bias voltage matching ratio | VAIO / VBIO | -1 |  | 1 | % | AIO, BIO floating, DIN = VCC | 8 |
| Receiver front-edge threshold | VLEAD | 0.85 | 1 | 1.15 | V | VTVL = 1.0V, HPEN = VCC | 8 |
| Receiver trailing-edge threshold | VTRAIL | 0.35 | 0.5 | 0.65 | V | VTVT = 0.5V, HPEN = VCC | 8 |
| TVL, TVT input leakage current | ITHLEAK | -1 |  | 1 | μA | TVL and TVT disconnected from resistor string, VTVL = VTVT = 2.5V | 8 |
| Input logic high level | VIH | 1.4 |  |  | V |  | 8 |
| Input logic low level | VIL |  |  | 0.4 | V |  | 8 |
| Input leakage current | ILEAK | -1 |  | 1 | μA |  | 8 |
| Open-drain logic low level | VOL |  |  | 0.3 | V | ISINK = 2mA | 8 |
| Open-drain leakage current | IODL |  |  | 1 | μA | DOUT open-circuit state, measuring leakage current | 8 |
| Output leading-edge rise time | tRLD | 0.8 | 1.4 | 2 | μs | RSRA = 120kΩ, RLOAD = 200Ω, see Fig 9-1 | 9 |
| Output leading-edge fall time | tFLD | 0.8 | 1.4 | 2 | μs | RSRA = 120kΩ, RLOAD = 200Ω, see Fig 9-1 | 9 |
| Output trailing-edge rise time | tRTR | 0.8 | 1.4 | 2 | μs | RSRA = 120kΩ, RLOAD = 200Ω, see Fig 9-1 | 9 |
| Output trailing-edge fall time | tFTR | 0.8 | 1.4 | 2 | μs | RSRA = 120kΩ, RLOAD = 200Ω, see Fig 9-1 | 9 |
| Transmit output symmetry | tSYM | -0.4 | 0 | 0.4 | μs |  | 9 |
| Terminal switch delay | tTERM | 0.3 |  | 0.5 | μs | RSRA = 120kΩ, RLOAD = 200Ω, see Fig 9-2 | 9 |
| Terminal on-time (DTA floating) | tTRMON | 19 | 34 | 63 | μs | RSRA = 120kΩ, RLOAD = 200Ω, DTA floating | 9 |
| Minimum terminal on-time | tTRMON_min | 10 |  |  | μs | RSRA = 120kΩ, RLOAD = 200Ω, DTA connected 10kΩ resistor | 9 |
| Maximum terminal on-time | tTRMON_max |  |  | 450 | μs | RSRA = 120kΩ, RLOAD = 200Ω, DTA connected 500kΩ resistor | 9 |
| Receiver propagation delay | tRPROP | 0.4 |  | 1 | μs | HPEN = VCC, see Fig 9-3 | 9 |
| Transmission propagation delay | tTPROP |  | 1 |  | μs |  | 9 |
| Receiver high-pass filter time | tHP |  | 1200 |  | μs | RST = VCC, HPEN = GND | 9 |

## CAD (KiCad official)

- Symbol: `CA-IF42088`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`
- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `ca-if42088-etched.step` / `ca-if42088-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ca-if42088.step` / `ca-if42088.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Chipanalog datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603012604839141376) (25 pp, sha256 `122d2f62121b39bf`, retrieved 2026-10-29, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ca-if42088-datasheet.pdf)