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CA-IF1051HS

Public Made by Adom

by adom

Chipanalog CAN Transceivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CA-IF1051HS

Chipanalog · CAN Transceivers · SOIC-8

CA-IF1051HS from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input: driving TXD high puts the bus driver in recessive state and driving it low puts it in dominant state, with an internal pull-up to VIO (floating TXD is pulled to the recessive state).
2 GND power_in Ground pin for the device; the datasheet's pin table text reads 'data input', which appears to be a translation error for ground.
3 VCC power_in 5 V supply input, recommended operating range 4.5 V to 5.5 V, with a 0.1 uF capacitor placed as close to the device as possible between VCC and GND.
4 RXD output Receive data output referenced to VIO: it is high when CANH and CANL are recessive (or open/shorted) and low when the bus is dominant, with output current limited to ±2 mA recommended and ±8 mA absolute maximum.
5 NC unconnected No connection.
6 CANL bidirectional Low-level CAN bus line, the low side of the transceiver bus I/O, rated for bus voltage of -70 V to +70 V on H-suffix devices.
7 CANH bidirectional High-level CAN bus line, the high side of the transceiver bus I/O, rated for bus voltage of -70 V to +70 V on H-suffix devices.
8 S input Mode select input: high selects silent mode (driver off, receiver on) and low or open selects normal mode.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC 5-V bus supply voltage (absolute maximum) VCC -0.3 7 V 5
CAN bus IO voltage (CANH, CANL), H-suffix device VBUS -70 70 V H-suffix device 5
Maximum differential voltage CANH to CANL, H-suffix device V(DIFF) -70 70 V H-suffix device 5
Logic-side input voltage (TXD, S) V(Logic_Input) -0.3 7 V 5
Logic-side output voltage (RXD) V(Logic_Output) -0.3 7 V 5
RXD receiver output current IO(RXD) -8 8 mA 5
Junction temperature TJ -55 150 °C 5
Storage temperature TSTG -65 150 °C 5
5-V bus supply voltage (recommended operating) VCC 4.5 5.5 V 6
RXD port high-level output current (recommended) IOH(RXD) -2 mA 6
RXD port low-level output current (recommended) IOL(RXD) 2 mA 6
5 V supply current, dominant Icc 40 60 mA TXD=0V, RL=60 Ohm（显性） 7
5 V supply current, dominant Icc 45 80 mA TXD=0V, RL=50 Ohm（显性） 7
5 V supply current, recessive Icc 1.5 2.5 mA TXD=Vcc, RL=50 Ohm（隐性） 7
5 V supply current, silent mode Icc 1.5 2.5 mA S=Vcc（静默模式） 7
Vcc UVLO voltage, rising Vuv_vcc 4.2 4.4 V 7
Vcc UVLO voltage, falling Vuv_vcc 3.8 4 4.25 V 7
Mode select S input low-level leakage current IIL -2 2 uA S=0V，Vcc=Vio=5.5V 7
Mode select S input leakage when unpowered Ilek(off) -1 1 uA S=5.5V, Vcc=Vio=0V 7
TXD input high-level leakage current IIH -2.5 0 1 uA S=Vcc 或者 Vio=5.5V 7
TXD input low-level leakage current IIL -100 -25 -7 uA S=0V，Vcc=Vio=5.5V 7
TXD input leakage when unpowered Ilek(off) -1 0 1 uA S=5.5V, Vcc=Vio=0V 7
RXD output high-level voltage (non-V suffix) VOH 4 4.6 V 不带有”V”后缀(只有 5V), Io=-2mA 7
RXD output low-level voltage (non-V suffix) VOL 0.2 0.4 V 不带有”V”后缀(只有 5V), Io=+2mA 7
RXD output leakage when unpowered Ilek(off) -1 0 1 uA S=5.5V, Vcc=Vio=0V 7
Single-ended dominant output voltage, CANH VO(DOM) 2.75 4.5 V TXD=低，S=0V, RL=50-65Ohm, CANH 端口 7
Single-ended dominant output voltage, CANL VO(DOM) 0.5 2.25 V TXD=低，S=0V, RL=50-65Ohm, CANL 端口 7
Differential dominant output voltage V O(DOM) 1.5 3 V TXD=低，RL=60 Ohm , RCM =165 Ohm, -5V=<VCM <=+10V 7
Differential dominant output voltage V O(DOM) 1.4 3 V TXD=低，RL=45-50 Ohm , RCM open 7
Differential dominant output voltage V O(DOM) 1.5 5 V TXD=低，RL=2240 Ohm , RCM open 7
Single-ended recessive output voltage, CANH VO(REC) 2 3 V TXD=高，无负载, CANH 端口 7
Single-ended recessive output voltage, CANL VO(REC) 2 3 V TXD=高，无负载, CANL 端口 7
Differential recessive output voltage VOD(REC) -120 12 mV TXD=高，S=0V, RL=60 Ohm 8
Differential recessive output voltage VOD(REC) -50 50 mV TXD=高，S=0V, 无负载 8
Short-circuit current, recessive IOS(SS_rec) -5 5 mA TXD=高，VBUS 从-27V 到 32V 8
Transient symmetry (dominant and recessive) Vsys 0.9 1.1 V/V RL=60 Ohm, RCM open,Txd=250k Hz,1M Hz 8
DC symmetry (dominant and recessive) Vsys_dc -0.4 0.4 V RL=60 Ohm, RCM open 8
Common-mode input voltage range VCM -30 30 V CANH 或者 CANL 到地，RXD 输出有效 8
CANH/CANL input resistance RIN 15 40 K OHm TXD=高，Vcm 从 -30V 到 30V 8
Differential input resistance RDIFF 30 80 K OHm TXD=高，Vcm 从 -30V 到 30V 8
Input resistance matching RDIFF(M) -2 2 % CANH=CANL=5V 8
Input capacitance, CANH or CANL to ground CIN 24 30 pF CANH 或者 CANL 到地 8
Differential input capacitance, CANH to CANL CIN_DIFF 12 15 pF CANH 到 CANL 8
Fault protection range, CANH or CANL to ground VFAULT -70 70 V CANH 或者 CANL 到地 9
TXD dominant timeout tDOM 1.2 3.8 ms RL=60 Ohm,CL open 8
Loop delay, recessive to dominant Tloop1 100 160 ns 隐性到显性, RL=60 Ohm,CL=100pF 8
Loop delay, dominant to recessive Tloop2 110 175 ns 显性到隐性, RL=60 Ohm,CL=100pF 8
Mode switching time (silent to normal or normal to silent) tONTXD 1 10 us 从静默态到常态或者从常态到静默态 8
Bit time, bus side Tbit（bus） 435 530 ns 总线侧 RL=60 Ohm,CL=100pF, CLrx=15pF 8
Bit time, receive side Tbit（rxd） 400 550 ns 接受侧 RL=60 Ohm,CL=100pF, CLrx=15pF 8
Receiver pulse deviation Trec -65 40 ns 接受侧 RL=60 Ohm,CL=100pF, CLrx=15pF 8
Common-mode input range, recessive threshold (TXD=high, Vcm -30 V to 30 V) VDIFF_R 0.4 V TXD=高, Vcm 从 -30V 到 30V 8
Differential input threshold, dominant (TXD=high, Vcm -30 V to 30 V) VDIFF_D 1 V TXD=高，Vcm 从 -30V 到 30V 8
Differential input hysteresis VDIFF_(HYST) 120 mV 8
TXD input high-level voltage (non-V suffix, 5 V only) VIH 2 V 不带有”V”后缀(只有 5V) 7
TXD input low-level voltage (non-V suffix, 5 V only) VIL 0.8 V 不带有”V”后缀(只有 5V) 7
Dominant-state current, CANH=-12V Icc 180 mA TXD=0V, CANH=-12V（显性） 7
Thermal resistance, junction to ambient (SOIC) RθJA 100 °C/W 6
Thermal resistance, junction to case (top) (SOIC) RθJC(top) 40 °C/W 6

CAD (KiCad official)

  • Symbol: CA-IF1051HS
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ca-if1051hs-etched.step / ca-if1051hs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-if1051hs.step / ca-if1051hs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (17 pp, sha256 8e4d7bbcf69ad3c6, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF