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CA-HP6050S

Public Made by Adom

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Chipanalog Voltage References, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower managementca-hp6050sfactory-2.0.0extractor-text

Verified CA-HP6050S

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CA-HP6050S · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 14-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-x7xf6ot2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ca-hp6050s.kicad_sym✓ ca-hp6050s.kicad_mod✓ ca-hp6050s.step
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Contents

README

markdown

CA-HP6050S

Chipanalog · Voltage References · SOIC-8

CA-HP6050S from Chipanalog, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DNC unconnected Do not connect; leave this pin unconnected.
2 VIN power_in Input supply voltage, 6V to 16V recommended for CA-HP6050 (absolute maximum 16V).
3 NR passive Noise reduction pin: a capacitor to GND can be connected to reduce wideband noise, and it may be left floating when unused.
4 GND power_in Ground.
5 TRIM passive Output voltage trim pin for external adjustment via a 10kOhm potentiometer from VOUT to GND with series resistor R1 (750K gives ±0.3% range, 1500K gives ±0.15% for CA-HP6050).
6 OUT power_out Reference voltage output of 5V with ±15mA drive capability and 0.1µF to 10µF external bypass capacitor supported.
7 DNC unconnected Do not connect; leave this pin unconnected.
8 DNC unconnected Do not connect; leave this pin unconnected.

Key specifications

Parameter Value
Manufacturer Chipanalog
Package SOIC-8
Category Power Management
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage (Grade A) VOUT 4.9975 5 5.0025 V VIN=10V, TA=25℃ 7
Initial accuracy (Grade A) VOERR 2.5 mV Grade A 7
Initial accuracy (Grade A) VOERR 0.05 % Grade A 7
Temperature drift coefficient (Grade A) TCVOUT 2.5 5 ppm/°C Grade A 7
Line regulation ΔVOUT/ΔVIN 2 30 ppm/V VIN=6 到 16V;−40℃ < TA < +125℃ 7
Load regulation ΔVOUT/ΔILOAD 7 15 ppm/mA ILOAD=-15mA 到 15mA，VIN=10V，−40℃ < TA < +125℃ 7
Output current capability ILOAD -15 15 mA 7
Quiescent current IIN 0.65 1 mA 无负载，−40℃ < TA < +125℃ 7
Noise voltage eNP-P 20 µVP-P 0.1 Hz 到 10 Hz 7
Noise voltage eNP-P 3.5 µVRMS 10 Hz 到 1 KHz 7
Turn-on settling time Ton 1 mS 建立到终值的±0.1%以内 7
Thermal hysteresis, first cycle 70 ppm TA=25℃，25℃>125℃>-40℃>25℃，第一周期 7
Thermal hysteresis, second cycle 40 ppm TA=25℃，25℃>125℃>-40℃>25℃，第二周期 7
Long-term stability ΔVOUT/t 30 ppm TA=35℃，1000 小时 7
Supply voltage VIN 6 16 V CA-HP6050 5
Ambient temperature TA -40 125 °C 5
Supply voltage VIN -0.3 16 V 5
Operating temperature -40 125 °C 5
Junction temperature 150 °C 5
Storage temperature range TSTG -65 150 °C 5
ESD HBM VESD -2000 2000 V ANSI/ESDA/JEDEC JS-001, all pins 5
ESD CDM VESD -500 500 V JEDEC JESD22-C101, all pins 5
Junction-to-ambient thermal resistance RθJA 120 °C/W SOIC8, 8 pins 5

CAD (KiCad official)

  • Symbol: CA-HP6050S
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ca-hp6050s-etched.step / ca-hp6050s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ca-hp6050s.step / ca-hp6050s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Chipanalog datasheet (14 pp, sha256 b35f479555e9a0a2, retrieved 2026-10-31, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF