component
C8051F850-C-GMR
Public Made by Adomby adom
SKYWORKS SILICON LABS Microcontrollers (MCU/MPU/SOC), QFN-20-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownC8051F850-C-GMR
SKYWORKS SILICON LABS · Microcontrollers (MCU/MPU/SOC) · QFN-20-EP(3x3)
C8051F850-C-GMR from SKYWORKS SILICON LABS, in a QFN-20-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.1/AGND | bidirectional | Port 0 bit 1 standard I/O, crossbar-capable, 5 V tolerant, with P0MAT.1, INT0.1/INT1.1, ADC0.1, CP0P.1/CP0N.1 functions, or optional AGND analog ground reference. |
| 2 | P0.0/VREF | bidirectional | Port 0 bit 0 standard I/O, crossbar-capable, with P0MAT.0, INT0.0/INT1.0, ADC0.0, CP0P.0/CP0N.0 functions, or optional external VREF input. |
| 3 | GND | power_in | Ground. |
| 4 | VDD | power_in | Power supply pin; device is specified for 2.2 to 3.6 V operation. |
| 5 | RST/C2CK | bidirectional | Active-low reset input and C2 debug clock. |
| 6 | P2.0/C2D | bidirectional | Standard I/O P2.0 shared with the bidirectional C2 debug data signal. |
| 7 | P1.6 | bidirectional | Port 1 bit 6 standard I/O, crossbar-capable, with P1MAT.6, ADC0.14, CP1P.6/CP1N.6 functions. |
| 8 | P1.5 | bidirectional | Port 1 bit 5 standard I/O, crossbar-capable, with P1MAT.5, ADC0.13, CP1P.5/CP1N.5 functions. |
| 9 | P1.4 | bidirectional | Port 1 bit 4 standard I/O, crossbar-capable, with P1MAT.4, ADC0.12, CP1P.4/CP1N.4 functions. |
| 10 | P1.3 | bidirectional | Port 1 bit 3 standard I/O, crossbar-capable, with P1MAT.3, ADC0.11, CP1P.3/CP1N.3 functions. |
| 11 | P1.2 | bidirectional | Port 1 bit 2 standard I/O, crossbar-capable, with P1MAT.2, ADC0.10, CP1P.2/CP1N.2 functions. |
| 12 | GND | power_in | Ground. |
| 13 | P1.1 | bidirectional | Port 1 bit 1 standard I/O, crossbar-capable, with P1MAT.1, ADC0.9, CP1P.1/CP1N.1 functions. |
| 14 | P1.0 | bidirectional | Port 1 bit 0 standard I/O, crossbar-capable, with P1MAT.0, ADC0.8, CP1P.0/CP1N.0 functions. |
| 15 | P0.7 | bidirectional | Port 0 bit 7 standard I/O, crossbar-capable, with P0MAT.7, INT0.7/INT1.7, ADC0.7, CP0P.7/CP0N.7 functions. |
| 16 | P0.6 | bidirectional | Port 0 bit 6 standard I/O, crossbar-capable, with P0MAT.6, CNVSTR, INT0.6/INT1.6, ADC0.6, CP0P.6/CP0N.6 functions. |
| 17 | P0.5 | bidirectional | Port 0 bit 5 standard I/O, crossbar-capable, with P0MAT.5, INT0.5/INT1.5, ADC0.5, CP0P.5/CP0N.5 functions; UART0 RX is always assigned here. |
| 18 | P0.4 | bidirectional | Port 0 bit 4 standard I/O, crossbar-capable, with P0MAT.4, INT0.4/INT1.4, ADC0.4, CP0P.4/CP0N.4 functions; UART0 TX is always assigned here. |
| 19 | P0.3 | bidirectional | Port 0 bit 3 standard I/O, crossbar-capable, with P0MAT.3, EXTCLK, INT0.3/INT1.3, ADC0.3, CP0P.3/CP0N.3 functions. |
| 20 | P0.2 | bidirectional | Port 0 bit 2 standard I/O, crossbar-capable, with P0MAT.2, INT0.2/INT1.2, ADC0.2, CP0P.2/CP0N.2 functions. |
| 21 | GND | power_in | Ground, exposed center pad of the QFN-20 package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS SILICON LABS |
| Package | QFN-20-EP(3x3) |
| Category | Embedded Processors & Controllers |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Supply Voltage on VDD | VDD | 2.2 | 3.6 | V | 8 | ||
| System Clock Frequency | fSYSCLK | 0 | 25 | MHz | 8 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | Commercial Grade Devices (-GM, -GS, -GU) | 8 | |
| Digital Core Supply Current, Normal Mode full speed | IDD | 4.45 | 4.85 | mA | Normal mode, code executing from flash; FSYSCLK = 24.5 MHz; -Gx devices | 8 | |
| Digital Core Supply Current, Normal Mode | IDD | 915 | 1150 | µA | Normal mode, code executing from flash; FSYSCLK = 1.53 MHz; -Gx devices | 8 | |
| Digital Core Supply Current, Normal Mode | IDD | 250 | 290 | µA | Normal mode, code executing from flash; FSYSCLK = 80 kHz, TA = 25 °C; -Gx devices | 8 | |
| Digital Core Supply Current, Normal Mode | IDD | 250 | 380 | µA | Normal mode, code executing from flash; FSYSCLK = 80 kHz; -Gx devices | 8 | |
| Digital Core Supply Current, Idle Mode | IDD | 2.05 | 2.3 | mA | Idle mode, core halted with peripherals running; FSYSCLK = 24.5 MHz; -Gx devices | 8 | |
| Digital Core Supply Current, Idle Mode | IDD | 550 | 700 | µA | Idle mode, core halted with peripherals running; FSYSCLK = 1.53 MHz; -Gx devices | 8 | |
| Digital Core Supply Current, Idle Mode | IDD | 125 | 130 | µA | Idle mode, core halted with peripherals running; FSYSCLK = 80 kHz, TA = 25 °C; -Gx devices | 8 | |
| Digital Core Supply Current, Idle Mode | IDD | 125 | 200 | µA | Idle mode, core halted with peripherals running; FSYSCLK = 80 kHz; -Gx devices | 8 | |
| Digital Core Supply Current, Stop Mode | IDD | 105 | 120 | µA | Stop mode, internal LDO ON, TA = 25 °C; -Gx devices | 8 | |
| Digital Core Supply Current, Stop Mode | IDD | 105 | 170 | µA | Stop mode, internal LDO ON; -Gx devices | 8 | |
| ADC0 Always-on Supply Current | IADC | 845 | 1200 | µA | 800 ksps 10-bit or 200 ksps 12-bit conversions; normal bias settings; VDD = 3.0 V | 8 | |
| ADC0 Always-on Supply Current | IADC | 425 | 580 | µA | 250 ksps 10-bit or 62.5 ksps 12-bit conversions; low power bias settings; VDD = 3.0 V | 8 | |
| Offset Error | EOFF | -3 | 0 | 3 | LSB | 12 Bit Mode, VREF = 1.65 V | 14 |
| Offset Error | EOFF | -2 | 0 | 2 | LSB | 10 Bit Mode, VREF = 1.65 V | 14 |
| Slope Error | EM | -0.1 | 0.02 | 0.1 | % | 12 Bit Mode | 14 |
| Slope Error | EM | -0.24 | 0.06 | 0.24 | % | 10 Bit Mode | 14 |
| Signal-to-Noise | SNR | 61 | 66 | dB | 12 Bit Mode; 10 kHz sine wave input 1 dB below full scale, max throughput, using AGND pin | 14 | |
| Signal-to-Noise | SNR | 53 | 60 | dB | 10 Bit Mode; 10 kHz sine wave input 1 dB below full scale, max throughput, using AGND pin | 14 | |
| Signal-to-Noise Plus Distortion | SNDR | 61 | 66 | dB | 12 Bit Mode; 10 kHz sine wave input 1 dB below full scale, max throughput, using AGND pin | 14 | |
| Signal-to-Noise Plus Distortion | SNDR | 53 | 60 | dB | 10 Bit Mode; 10 kHz sine wave input 1 dB below full scale, max throughput, using AGND pin | 14 | |
| Internal Fast Settling Reference Output Voltage | VREFFS | 1.62 | 1.65 | 1.68 | V | Full temperature and supply range; 1.65 V setting | 15 |
| Internal Fast Settling Reference Output Voltage | VREFFS | 2.35 | 2.4 | 2.45 | V | Full temperature and supply range; 2.4 V setting, VDD > 2.6 V | 15 |
| Turn-on Time | tREFFS | 1.5 | µs | 15 | |||
| Ambient Temperature Under Bias | TBIAS | -55 | 125 | °C | 22 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | 22 | ||
| Voltage on VDD | VDD | -0.3 | 4.2 | V | Referenced to GND (printed as GND-0.3) | 22 | |
| Voltage on I/O pins or RST | VIN | -0.3 | 5.8 | V | VDD > 3.3 V; referenced to GND (printed as GND-0.3) | 22 | |
| Voltage on I/O pins or RST | VIN | -0.3 | V | VDD < 3.3 V; max printed as VDD+2.5 V; min referenced to GND (printed as GND-0.3) | 22 | ||
| Total Current Sunk into Supply Pin | IVDD | 400 | mA | 22 | |||
| Total Current Sourced out of Ground Pin | IGND | 400 | mA | 22 | |||
| Current Sourced or Sunk by Any I/O Pin or RST | IPIO | -100 | 100 | mA | 22 | ||
| Operating Junction Temperature | TJ | -40 | 105 | °C | Commercial Grade Devices (-GM, -GS, -GU) | 22 | |
| Thermal Resistance, QFN-20 packages | JA | 60 | °C/W | 21 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body | 45 |
CAD (KiCad official)
- Symbol:
C8051F850-C-GMR - Footprint:
Package_DFN_QFN:UQFN-20-1EP_3x3mm_P0.4mm_EP1.85x1.85mm - 3D model: QFN-20-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
c8051f850-c-gmr-etched.step/c8051f850-c-gmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);c8051f850-c-gmr.step/c8051f850-c-gmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SKYWORKS SILICON LABS datasheet (313 pp, sha256
f06cd3edf17e3279, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).