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C8051F585-IQ

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SILICON LABS Pre-ordered MCUs, TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersc8051f585-iqfactory-2.0.0extractor-text

Verified C8051F585-IQ

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier lcsc, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: C8051F585-IQ · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 361-page datasheet
  • ✓distributor: lcsc C1337786, digikey 336-1574-ND, mouser 634-C8051F585-IQ
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ga7bwfor/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.31)
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 59 kB, viewers/symbol.html 32 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ c8051f585-iq.kicad_sym✓ c8051f585-iq.kicad_mod✓ c8051f585-iq.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers c8051f585-iq: viewers · Ray
c8051f585-iq-etched.glb c8051f585-iq: factory component page (tier=lcsc) · Ray
c8051f585-iq-etched.step c8051f585-iq: factory component page (tier=lcsc) · Ray
c8051f585-iq-hero.glb c8051f585-iq: hero GLB from the etched model (keeps the MPN mark) · Ray
c8051f585-iq-hero.overlay.json c8051f585-iq: hero GLB from the etched model (keeps the MPN mark) · Ray
c8051f585-iq.glb Publish 0.1.0 · Ray
c8051f585-iq.kicad_mod Publish 0.1.0 · Ray
c8051f585-iq.kicad_sym Publish 0.1.0 · Ray
c8051f585-iq.lbr Publish 0.1.0 · Ray
c8051f585-iq.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 48 pins · Ray

C8051F585-IQ

SILICON LABS · Pre-ordered MCUs · TQFP-48(7x7)

C8051F585-IQ from SILICON LABS, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.1 bidirectional Port 0.1 is a digital I/O or analog input pin; when the ADC uses the external CNVSTR start-of-conversion source, its PnSKIP bit must be set to 1.
2 VIO power_in Port I/O supply voltage that must be connected; setting VIO to 5 V lets the Port I/O and RST pins interface to 5 V logic.
3 VREGIN power_in Voltage Regulator Input for the on-chip voltage regulator (REG0).
4 VDD power_in Digital supply voltage that must be connected; the device is specified for 1.8 V to 5.25 V operation.
5 VDDA power_in Analog supply voltage that must be connected.
6 GND power_in Digital ground that must be connected.
7 GNDA power_in Analog ground that must be connected.
8 P0.0 bidirectional Port 0.0 is a digital I/O or analog input pin that doubles as the VREF voltage reference; if used as VREF it must be set to analog I/O and skipped by the Crossbar.
9 P4.7 bidirectional Port 4.7 is a digital-only I/O pin (no analog input or PnSKIP option) with output mode set by PnMDOUT and it is also used by the External Memory Interface when enabled.
10 P4.6 bidirectional Port 4.6 is a digital-only I/O pin (no analog input or PnSKIP option) with output mode set by PnMDOUT and it is also used by the External Memory Interface when enabled.
11 C2D bidirectional Bi-directional data signal for the C2 Debug Interface.
12 RST/C2CK bidirectional Device reset: an open-drain output of the internal POR or VDD monitor that an external source can drive low to reset the device, and the clock input for the C2 Debug Interface.
13 P4.5 bidirectional Port 4.5 is a digital-only I/O pin (no analog input or PnSKIP option) with output mode set by PnMDOUT and it is also used by the External Memory Interface when enabled.
14 P4.4 bidirectional Port 4.4 is a digital-only I/O pin (no analog input or PnSKIP option) with output mode set by PnMDOUT and it is also used by the External Memory Interface when enabled.
15 P4.3 bidirectional Port 4.3 is a digital-only I/O pin (no analog input or PnSKIP option) with output mode set by PnMDOUT and it is also used by the External Memory Interface when enabled.
16 P4.2 bidirectional Port 4.2 is a digital-only I/O pin (no analog input or PnSKIP option) with output mode set by PnMDOUT and it is also used by the External Memory Interface when enabled.
17 P4.1 bidirectional Port 4.1 is a digital-only I/O pin (no analog input or PnSKIP option) with output mode set by PnMDOUT and it is also used by the External Memory Interface when enabled.
18 P4.0 bidirectional Port 4.0 is a digital-only I/O pin (no analog input or PnSKIP option) with output mode set by PnMDOUT and it is also used by the External Memory Interface when enabled.
19 P3.7 bidirectional Port 3.7 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
20 P3.6 bidirectional Port 3.6 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
21 P3.5 bidirectional Port 3.5 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
22 P3.4 bidirectional Port 3.4 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
23 P3.3 bidirectional Port 3.3 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
24 P3.2 bidirectional Port 3.2 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
25 P3.1 bidirectional Port 3.1 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
26 P3.0 bidirectional Port 3.0 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
27 P2.7 bidirectional Port 2.7 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
28 P2.6 bidirectional Port 2.6 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
29 P2.5 bidirectional Port 2.5 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
30 P2.4 bidirectional Port 2.4 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
31 P2.3 bidirectional Port 2.3 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
32 P2.2 bidirectional Port 2.2 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
33 P2.1 bidirectional Port 2.1 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
34 P2.0 bidirectional Port 2.0 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT, and it is also used by the External Memory Interface when enabled.
35 P1.7 bidirectional Port 1.7 is a digital I/O or analog input pin, and is the EMIF /WR control line when the External Memory Interface is used (Crossbar must skip it).
36 P1.6 bidirectional Port 1.6 is a digital I/O or analog input pin, and is the EMIF /RD control line when the External Memory Interface is used (Crossbar must skip it).
37 P1.5 bidirectional Port 1.5 is a digital I/O or analog input pin, and is the EMIF ALE control line in multiplexed EMIF mode (Crossbar must skip it).
38 P1.4 bidirectional Port 1.4 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT.
39 P1.3 bidirectional Port 1.3 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT.
40 P1.2 bidirectional Port 1.2 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT.
41 P1.1 bidirectional Port 1.1 is a digital I/O or analog input pin, with input mode set by PnMDIN and output mode by PnMDOUT.
42 P1.0 bidirectional Port 1.0 is a digital I/O or analog input pin that can also be selected as the INT0/INT1 external interrupt source via IT01CF.
43 P0.7 bidirectional Port 0.7 is a digital I/O or analog input pin; the Crossbar fixes CAN0 RX to this pin when CAN0 is enabled.
44 P0.6 bidirectional Port 0.6 is a digital I/O or analog input pin; the Crossbar fixes CAN0 TX to this pin when CAN0 is enabled.
45 P0.5 bidirectional Port 0.5 is a digital I/O pin; the Crossbar always assigns UART0 RX to this pin.
46 P0.4 bidirectional Port 0.4 is a digital I/O pin; the Crossbar always assigns UART0 TX to this pin.
47 P0.3 bidirectional Port 0.3 is a digital I/O or analog input pin that serves as XTAL2 for the external oscillator, so its PnSKIP bit must be set when the oscillator is used.
48 P0.2 bidirectional Port 0.2 is a digital I/O or analog input pin that serves as XTAL1 for the external oscillator, so its PnSKIP bit must be set when the oscillator is used.

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient Temperature under Bias -55 135 °C 41
Storage Temperature -65 150 °C 41
Voltage on VREGIN with Respect to GND -0.3 5.5 V 41
Voltage on VDD with Respect to GND -0.3 2.8 V 41
Voltage on VDDA with Respect to GND -0.3 2.8 V 41
Voltage on VIO with Respect to GND -0.3 5.5 V 41
Maximum Total Current through VREGIN or GND 500 mA 41
Maximum Output Current Sunk by RST or any Port Pin 100 mA 41
Maximum Output Current Sourced by any Port Pin 100 mA 41
Supply Input Voltage (VREGIN) 1.8 5.25 V -40 to +125 °C, 24 MHz system clock unless otherwise specified 42
Digital Supply Voltage (VDD) VDD 2.75 V System Clock < 25 MHz; minimum printed as VRST (see Table 5.4) 42
Analog Supply Voltage (VDDA) VDDA 2.75 V System Clock < 25 MHz; minimum printed as VRST (see Table 5.4) 42
Port I/O Supply Voltage (VIO) VIO 1.82 5.25 V Normal Operation 42
SYSCLK (System Clock) SYSCLK 0 50 MHz 42
Specified Operating Temperature Range -40 125 °C 42
Digital Supply Current, CPU Active (IDD) IDD 8.5 11 mA VDD = 2.1 V, F = 25 MHz 42
Digital Supply Current, CPU Active (IDD) IDD 15 21 mA VDD = 2.1 V, F = 50 MHz 42
Digital Supply Current, CPU Active (IDD) IDD 12 21 mA VDD = 2.6 V, F = 25 MHz 43
Digital Supply Current, CPU Active (IDD) IDD 21 33 mA VDD = 2.6 V, F = 50 MHz 43
Digital Supply Current, CPU Inactive (Idle Mode) (IDD) IDD 5.8 8 mA VDD = 2.1 V, F = 25 MHz 44
Digital Supply Current, CPU Inactive (Idle Mode) (IDD) IDD 11 16 mA VDD = 2.1 V, F = 50 MHz 44
Digital Supply Current, CPU Inactive (Idle Mode) (IDD) IDD 7.3 15 mA VDD = 2.6 V, F = 25 MHz 44
Digital Supply Current, CPU Inactive (Idle Mode) (IDD) IDD 15 25 mA VDD = 2.6 V, F = 50 MHz 44
Output Low Voltage 50 mV VIO = 1.8 V: IOL = 70 µA 46
Output Low Voltage 750 mV VIO = 1.8 V: IOL = 8.5 mA 46
Output Low Voltage 45 mV VIO = 2.7 V: IOL = 70 µA 46
Output Low Voltage 550 mV VIO = 2.7 V: IOL = 8.5 mA 46
Output Low Voltage 40 mV VIO = 5.25 V: IOL = 70 µA 46
Output Low Voltage 400 mV VIO = 5.25 V: IOL = 8.5 mA 46
RST Input Pullup Current 45 115 µA RST = 0.0 V 47
VDD POR Threshold (VRST-LOW) VRST-LOW 1.65 1.75 1.8 V 47
VDD POR Threshold (VRST-HIGH) VRST-HIGH 2.25 2.3 2.45 V 47
VDD Ramp Time for Power On 1 ms VDD Ramp 0-1.8 V 47
Missing Clock Detector Timeout 200 390 600 µs Time from last system clock rising edge to reset initiation; VDD = 2.1 V 47
Missing Clock Detector Timeout 200 280 600 µs Time from last system clock rising edge to reset initiation; VDD = 2.5 V 47
Reset Time Delay 130 160 µs Delay between release of any reset source and code execution at location 0x0000 47
Minimum RST Low Time to Generate a System Reset 6 µs 47
VDD Monitor Turn-on Time 60 100 µs 47
VDD Monitor Supply Current 1 2 µA 47
Endurance 20 150 k Erase/Write 48
Flash Retention 10 years 85 °C 48
Erase Cycle Time 28 30 45 ms 25 MHz System Clock 48
Write Cycle Time 79 84 125 µs 25 MHz System Clock 48
Temperature during Programming Operations 0 125 °C -I Devices 48
Oscillator Frequency (VDD > VREGMIN) -0.5 0.5 % IFCN = 111b; nominal 24 MHz 48
Oscillator Frequency (VDD < VREGMIN) -1 1 % IFCN = 111b; nominal 24 MHz 48
Oscillator Supply Current (from VDD) 880 1300 µA Internal Oscillator On, OSCICN[7:6] = 11b 48
Input Frequency (Fcmin) Fcmin 2 MHz 49
Clock Multiplier Output Frequency 50 MHz 49
Clock Multiplier Power Supply Current 1.4 1.9 µA 49
Crystal Frequency 0.02 25 MHz 49
Input Voltage Range (VREGIN) VREGIN 1.8 5.25 V 49
Output Voltage (VDD) VDD 2 2.1 2.25 V 2.1 V operation (REG0MD = 0) 49
Output Voltage (VDD) VDD 2.5 2.6 2.75 V 2.6 V operation (REG0MD = 1) 49
ADC0 Offset Error -10 -1.6 10 LSB 50
Internal Reference Output Voltage 1.45 1.5 1.55 V 25 °C ambient (REFLV = 0) 51
Internal Reference Output Voltage 2.15 2.2 2.25 V 25 °C ambient (REFLV = 1), VDD = 2.6 V 51
Comparator Input Offset Voltage -10 10 mV 52

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body 31

CAD (KiCad official)

  • Symbol: C8051F585-IQ
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: c8051f585-iq-etched.step / c8051f585-iq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f585-iq.step / c8051f585-iq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (361 pp, sha256 43992a079d5dbe76, retrieved 2026-11-13, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF